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9DMU0441 の電気的特性と機能

9DMU0441のメーカーはIDTです、この部品の機能は「2:4 1.5V PCIe Gen1-2-3 Clock Mux」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DMU0441
部品説明 2:4 1.5V PCIe Gen1-2-3 Clock Mux
メーカ IDT
ロゴ IDT ロゴ 




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9DMU0441 Datasheet, 9DMU0441 PDF,ピン配置, 機能
2:4 1.5V PCIe Gen1-2-3 Clock Mux
w/Zo=100ohms
9DMU0441
DATASHEET
General Description
The 9DMU0441 is a member of IDT's SOC-Friendly 1.5V
Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. It has
integrated output terminations providing Zo=100ohms for
direct connection to 100ohm transmission lines. Each of the 4
outputs has its own dedicated OE# pin for optimal system
control and power management. The part provides
asynchronous and glitch-free switching modes.
Recommended Application
2:4 PCIe Gen1-2-3 clock multiplexer
Output Features
4 – Low-Power (LP) HCSL DIF pairs w/Zo=100
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Additive phase jitter @ 125MHz: 535fs rms typical (12kHz
to 20MHz)
DIF output-to-output skew <50ps
Features/Benefits
LP-HCSL outputs w/integrated terminations; saves 16
resistors compared to standard HCSL outputs
1.5V operation; 26mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 167MHz operating frequency
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
4
,
A
B
DIF3
DIF2
DIF1
DIF0
9DMU0441 REVISION A 09/24/14
1
©2014 Integrated Device Technology, Inc.

1 Page





9DMU0441 pdf, ピン配列
9DMU0441 DATASHEET
Pin Descriptions (cont.)
Pin# Pin Name
16 VDD1.5
17 DIF2
18 DIF2#
19 ^OE2#
20 DIF3
21 DIF3#
22 ^OE3#
23 ^SEL_A_B#
24 GNDR
25 EPAD
Type
PWR
OUT
OUT
IN
OUT
OUT
IN
IN
GND
GND
Pin Description
Power supply, nominally 1.5V
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Input to select differential input clock A or differential input clock B. This input has an internal
pull-up resistor.
0 = Input B selected, 1 = Input A selected.
Analog Ground pin for the differential input (receiver)
Connect to Ground.
REVISION A 09/24/14
3 2:4 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS


3Pages


9DMU0441 電子部品, 半導体
9DMU0441 DATASHEET
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage - DIF_IN VIHDIF
Input Low Voltage - DIF_IN
Input Common Mode
Voltage - DIF_IN
VILDIF
VCOM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
300
VSS - 300
200
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Peak to Peak value (VIHDIF - VILDIF)
Measured differentially
300
0.35
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
TYP
750
0
50
MAX
1150
UNITS NOTES
mV 1
300 mV 1
725
1450
8
5
55
150
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Slew rate matching
dV/dt
ΔdV/dt
Scope averaging on, fast setting
Slew rate matching, Scope averaging on
1.1 2.3 3.4 V/ns 1,2,3
12 20 % 1,2,4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 550 755 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 28 150
Max Voltage
Vmax
Measurement on single ended signal using
Min Voltage
Vmin
absolute value. (Scope averaging off)
Vswing
Vswing
Scope averaging off
Crossing Voltage (abs) Vcross_abs
Scope averaging off
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
761 1150 mV
-300 10
300 1455
mV
250 377 550 mV
10 140 mV
1,2
1,5
1,6
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
Electrical Characteristics–Current Consumption
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Operating Supply Current
IDD
VDD, All outputs active @100MHz
Powerdown Current
IDDPD
VDD, all outputs disabled
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
17
1.4
MAX
26
2.5
UNITS
mA
mA
NOTES
1
1, 2
2:4 1.5V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS
6
REVISION A 09/24/14

6 Page



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部品番号部品説明メーカ
9DMU0441

2:4 1.5V PCIe Gen1-2-3 Clock Mux

IDT
IDT


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