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PDF 9DMV0431 Data sheet ( Hoja de datos )
| Número de pieza | 9DMV0431 | |
| Descripción | 2:4 1.8V PCIe Gen1-2-3 Clock Mux | |
| Fabricantes | IDT | |
| Logotipo |  |
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2:4 1.8V PCIe Gen1-2-3 Clock Mux
9DMV0431
DATASHEET
General Description
The 9DMV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe Gen1-2-3 family. Each of the 4
outputs has its own dedicated OE# pin for optimal system
control and power management. The part provides
asynchronous and glitch-free switching modes.
Recommended Application
2:4 PCIe Gen1-2-3 clock multiplexer
Output Features
• 4 -Low-Power (LP) HCSL DIF pairs
Key Specifications
• DIF additive cycle-to-cycle jitter <5ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• Additive phase jitter @ 125MHz: 420fs rms typical (12kHz
to 20MHz)
• DIF output-to-output skew <50ps
Features/Benefits
• LP-HCSL outputs; save 8 resistors compared to standard
HCSL outputs
• 1.8V operation; 36mW typical power consumption
• Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
• Spread Spectrum Compatible; supports EMI reduction
• OE# pins; support DIF power management
• HCSL differential inputs; can be driven by common clock
sources
• 1MHz to 200MHz operating frequency
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
4
,
A
B
DIF3
DIF2
DIF1
DIF0
9DMV0431 REVISION B 01/26/15
1
©2015 Integrated Device Technology, Inc.
1 page  
9DMV0431 DATASHEET
Electrical Characteristics–Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5
3.3
150
125
UNITS NOTES
V 1,2
V 1,3
V1
°C 1
°C 1
V1
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
Ambient Operating
Temperature
TAMB
Industrial range
Input High Voltage
VIH
Single-ended inputs, except SMBus
Input Low Voltage
VIL
Single-ended inputs, except SMBus
Input Current
IIN Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IINP VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Input Frequency
Fin
Pin Inductance
Lpin
Capacitance
CIN
CINDIF_IN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
COUT
Output pin capacitance
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Input SS Modulation
Frequency non-PCIe
fMODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tfall tF Fall time of single-ended control inputs
Trise
tR Rise time of single-ended control inputs
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 DIF_IN input
1.7
-40
0.75 VDD
-0.3
-5
-200
1
1.5
1.5
30
0
1
1.8 1.9 V
25 85 °C
VDD + 0.3
0.25 VDD
5
V
V
uA
1
200 uA
200 MHz 2
7 nH 1
5 pF 1
2.7 pF 1,4
6 pF 1
1 ms 1,2
33 kHz
66 kHz
3 clocks 1,3
5 ns 2
5 ns 2
REVISION B 01/26/15
5 2:4 1.8V PCIE GEN1-2-3 CLOCK MUX
5 Page 
9DMV0431 DATASHEET
Ordering Information
Part / Order Number Shipping Packaging
9DMV0431AKILF
Tubes
9DMV0431AKILFT
Tape and Reel
Package
24-pin VFQFPN
24-pin VFQFPN
Temperature
-40 to +85° C
-40 to +85° C
"LF" to the suffix denotes Pb-Free configuration, RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev.
A
B
Initiator
RDW
RDW
Issue Date Description
1. Updated Electrical Tables with Char data
9/24/2014 2. Updated General Description
3. Move to final
1/26/2015 Updated package drawing and dimensions
Page #
Various
9
REVISION B 01/26/15
11 2:4 1.8V PCIE GEN1-2-3 CLOCK MUX
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 9DMV0431.PDF ] | |
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