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9DMU0131 の電気的特性と機能

9DMU0131のメーカーはIDTです、この部品の機能は「2:1 1.5V PCIe Gen1-2-3 Clock Mux」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DMU0131
部品説明 2:1 1.5V PCIe Gen1-2-3 Clock Mux
メーカ IDT
ロゴ IDT ロゴ 




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9DMU0131 Datasheet, 9DMU0131 PDF,ピン配置, 機能
2:1 1.5V PCIe Gen1-2-3 Clock Mux
9DMU0131
DATASHEET
General Description
The 9DMU0131 is a member of IDT's SOC-Friendly 1.5V
Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. The output
has an OE# pin for optimal system control and power
management. The part provides asynchronous or glitch-free
switching modes.
Recommended Application
2:1 1.5V PCIe Gen1-2-3 Clock Mux
Output Features
1 – Low-Power (LP) HCSL DIF pair
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
125MHz additive phase jitter 535fs rms typical (12kHz to
20MHz)
Features/Benefits
LP-HCSL output; saves 2 resistors compared to standard
HCSL output
1.5V operation; 11mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pin; supports DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 167MHz operating frequency
Space saving 16-pin 3x3mm VFQFPN; minimal board
space
Block Diagram
^OE0#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
A
DIF0
B
9DMU0131 REVISION A 09/30/14
1
©2014 Integrated Device Technology, Inc.

1 Page





9DMU0131 pdf, ピン配列
Test Loads
Low-Power HCSL Output Test Load
Rs
Low-Power HCSL
Output
Rs
Alternate Differential Output Terminations
Rs Zo Units
33 100 Ohms
27 85
Driving LVDS
Driving LVDS
Zo=100ohms
5 inches
2pF 2pF
3.3 Volts
Rs
Rs
Cc
Cc
R7a R7b
L4
R8a R8b
LVDS CLK
Input
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
9DMU0131 DATASHEET
REVISION A 09/30/14
3 2:1 1.5V PCIE GEN1-2-3 CLOCK MUX


3Pages


9DMU0131 電子部品, 半導体
9DMU0131 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Duty Cycle Distortion
tDCD
Measured differentially@100MHz
-1 -0.1 1
% 1,3
Skew, Input to Output
tpdBYP
Bypass Mode, VT = 50%
2166
2896
3952
ps
1
Skew, Output to Output
tsk3
VT = 50%
N/A N/A ps 1
Jitter, Cycle to cycle
tjcyc-cyc
Additive Jitter
0.1 8
ps 1,2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
Electrical Characteristics–Phase Jitter Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Additive Phase Jitter,
Bypass Mode
SYMBOL
CONDITIONS
tjphPCIeG1
tjphPCIeG2
tjphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
125MHz, 1.5MHz to 10MHz, -20dB/decade
tjph125M0 rollover < 1.5MHz, -40db/decade rolloff > 10MHz
MIN
TYP
0.4
0.4
0.1
0.05
365
MAX
5
0.55
0.2
0.1
380
INDUSTRY
LIMIT UNITS Notes
N/A ps (p-p) 1,2,3,5
N/A ps 1,2,3,4,
(rms)
5
N/A ps 1,2,3,4
(rms)
N/A
ps
(rms)
1,2,3,4
fs
N/A (rms) 1,6
tjph125M1
125MHz, 12KHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
535 550
N/A
1Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5 Driven by 9FGU0831 or equivalent
6 Rohde&Schartz SMA100
fs
(rms)
1,6
2:1 1.5V PCIE GEN1-2-3 CLOCK MUX
6
REVISION A 09/30/14

6 Page



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部品番号部品説明メーカ
9DMU0131

2:1 1.5V PCIe Gen1-2-3 Clock Mux

IDT
IDT


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