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854S057B の電気的特性と機能

854S057BのメーカーはIDTです、この部品の機能は「4:1 or 2:1 LVDS Clock Multiplexer」です。


製品の詳細 ( Datasheet PDF )

部品番号 854S057B
部品説明 4:1 or 2:1 LVDS Clock Multiplexer
メーカ IDT
ロゴ IDT ロゴ 




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854S057B Datasheet, 854S057B PDF,ピン配置, 機能
4:1 or 2:1 LVDS Clock Multiplexer with
Internal Input Termination
854S057B
Datasheet
General Description
The 854S057B is a 4:1 or 2:1 LVDS Clock Multiplexer which can
operate up to 2GHz. The PCLK, nPCLK pairs can accept most
standard differential input levels. Internal termination is provided on
each differential input pair. The 854S057B operates using a 2.5V
supply voltage. The fully differential architecture and low propagation
delay make it ideal for use in high speed multiplexing applications.
The select pins have internal pulldown resistors. Leaving one input
unconnected (pulled to logic low by the internal resistor) will
transform the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins will
select the same numbered data input (i.e., 00 selects PCLK0,
nPCLK0).
Features
High speed differential multiplexer. The device can be configured
as either a 4:1 or 2:1 multiplexer
One LVDS output pair
Four selectable PCLK, nPCLK inputs with internal termination
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2GHz
Part-to-part skew: 200ps (maximum)
Propagation delay: 800ps (maximum)
Additive phase jitter, RMS: 0.065ps (typical)
Full 2.5V power supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
VT0
50
PCLK0
nPCLK0
VT1
50
50
PCLK1
nPCLK1
50
VT2
50
PCLK2
nPCLK2
VT3
50
50 50
PCLK3
nPCLK3
SEL1 Pulldown
SEL0 Pulldown
00
01
10
11
Q
nQ
©2016 Integrated Device Technology, Inc.
Pin Assignment
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
1
2
3
4
5
6
7
8
9
10
20 VDD
19 PCLK3
18 VT3
17 nPCLK3
16 Q
15 nQ
14 PCLK2
13 VT2
12 nPCLK2
11 GND
854S057B
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
Top View
1 Revision B, February 10, 2016

1 Page





854S057B pdf, ピン配列
854S057B Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
4.6V
-0.5V to VDD + 0.5V
10mA
15mA
Input Current, PCLK, nPCLK
±50mA
VT Current, IVT
Package Thermal Impedance, JA
Storage Temperature, TSTG
±100mA
92.1°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VDD Power Supply Voltage
IDD Power Supply Current
2.375
2.5
Maximum
2.625
50
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Current SEL0, SEL1
IIL Input Low Current SEL0, SEL1
VDD = 2.5V
VDD = 2.5V
VDD = VIN = 2.625V
VDD = 2.625V, VIN = 0V
1.7
-0.3
-10
Typical
Maximum
VDD + 0.3
0.7
150
Units
V
V
µA
µA
Table 4C. LVPECL Differential DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
IIN
VPP
VCMR
Absolute Input Current; NOTE 1
Peak-to-Peak Voltage; NOTE 2
Common Mode Input Voltage; NOTE 2, 3
VDD = VIN = 2.625V
0.15
GND + 1.2
NOTE 1: Guaranteed by design.
NOTE 2: VIL should not be less than -0.3V.
NOTE 3: Common mode input voltage is defined as VIH.
Typical
Maximum
35
1.2
VDD
Units
mA
V
V
©2016 Integrated Device Technology, Inc.
3
Revision B, February 10, 2016


3Pages


854S057B 電子部品, 半導体
Parameter Measurement Information
2.5V±5%
POWER SUPPLY
+ Float GND –
VDD
SCOPE
Q
nQ
VDD
nPCLK[0:3]
PCLK[0:3]
V
PP
GND
854S057B Datasheet
Cross Points
V
CMR
LVDS Output Load AC Test Circuit
Differential Input Level
Spectrum of Output Signal Q
A0 MUX selects active
input clock signal
MUX_ISOL = A0 – A1
A1 MUX selects static input
MUX Isolation
ƒ
(fundamental)
Frequency
Part 1
nQ
Q
nQ Par t 2
Q
t sk(pp)
Part-to-Part Skew
nPCLKx
PCLKx
nPCLKy
PCLKy
nQ
Q
Input Skew
tPD2
tPD1
tsk(i)
tsk(i) = |tPD1 - tPD2|
nPCLK[0:3]
PCLK[0:3]
nQ
Q
tPD
Propagation Delay
©2016 Integrated Device Technology, Inc.
6
Revision B, February 10, 2016

6 Page



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部品番号部品説明メーカ
854S057B

4:1 or 2:1 LVDS Clock Multiplexer

IDT
IDT


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