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853S111B PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 853S111B
部品説明 LVPECL/ECL Fanout Buffer
メーカ IDT
ロゴ IDT ロゴ 



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853S111B Datasheet, 853S111B PDF,ピン配置, 機能
Low Skew, 1-to-10, Differential-to-2.5V,
3.3V LVPECL/ECL Fanout Buffer
853S111B
DATA SHEET
General Description
The 853S111B is a low skew, high performance 1-to-10
Differential-to-2.5V/ 3.3V LVPECL/ECL Fanout Buffer. The
853S111B is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the 853S111B ideal for those clock distribution
applications demanding well defined performance and repeatability.
Pin Assignments
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
24 23 22 21 20 19 18 17
25 16
26 853S111B 15
27 32-Lead TQFP, E-Pad 14
28 7mm x 7mm x 1mm 13
29 package body 12
30 Y Package 11
31 Top View 10
32 9
12 3 45 6 78
VCCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
VCCO
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
VCCO
24 23 22 21 20 19 18 17
25 16
26 853S111B 15
27 32-Lead VFQFN 14
28 5mm x 5mm x 0.925mm 13
29 package body 12
30 K Package 11
31 Top View 10
32 9
12 3 45 6 78
VCCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
VCCO
Features
Ten differential 2.5V, 3.3V LVPECL/ECL outputs
Two selectable differential input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, SSTL, CML
Maximum output frequency: 2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 645ps (maximum)
Additive Phase Jitter, RMS: 0.03ps (typical)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) packaging
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
CLK_SEL Pulldown
VBB
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
nQ3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
nQ8
nQ8
Q9
nQ9
853S111B REVISION E 6/30/15
1 ©2015 Integrated Device Technology, Inc.

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