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853S058 の電気的特性と機能

853S058のメーカーはIDTです、この部品の機能は「LVPECL/ECL Clock Multiplexer」です。


製品の詳細 ( Datasheet PDF )

部品番号 853S058
部品説明 LVPECL/ECL Clock Multiplexer
メーカ IDT
ロゴ IDT ロゴ 




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853S058 Datasheet, 853S058 PDF,ピン配置, 機能
8:1 Differential-to-3.3V or 2.5V
LVPECL/ECL Clock Multiplexer
853S058
DATA SHEET
General Description
The 853S058 is an 8:1 Differential-to-3.3V or 2.5V LVPECL / ECL
Clock Multiplexer which can operate up to 2.5 GHz. The 853S058
has 8 differential selectable clock inputs. The PCLK, nPCLK input
pairs can accept LVPECL, LVDS, SSTL or CML levels. The fully
differential architecture and low propagation delay make it ideal for
use in clock distribution circuits. The select pins have internal
pulldown resistors. The SEL2 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 000 selects PCLK0, nPCLK0).
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
PCLK2 Pulldown
nPCLK2 Pullup/Pulldown
PCLK3 Pulldown
nPCLK3 Pullup/Pulldown
PCLK4 Pulldown
nPCLK4 Pullup/Pulldown
PCLK5 Pulldown
nPCLK5 Pullup/Pulldown
PCLK6 Pulldown
nPCLK6 Pullup/Pulldown
PCLK7 Pulldown
nPCLK7 Pullup/Pulldown
000
(default)
001
010
011
100
101
110
111
Q
nQ
Features
High speed 8:1 differential muliplexer
One differential 3.3V or 2.5V LVPECL output pair
Eight selectable differential PCLKx, nPCLKx input pairs
Differential PCLKx, nPCLKx pairs can accept the following
interface levels: LVPECL, LVDS, SSTL,CML
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx input
Additive phase jitter, RMS: 0.075ps (typical)
Part-to-part skew: 350ps (maximum)
Propagation delay: 600ps (maximum)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
VCC
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
1
2
3
4
5
6
7
8
9
10
11
12
24 PCLK7
23 nPCLK7
22 PCLK6
21 nPCLK6
20 VCC
19 Q
18 nQ
17 VEE
16 PCLK5
15 nPCLK5
14 PCLK4
13 nPCLK4
853S058
24-Lead TSSOP, 173-MIL
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
SEL2 Pulldown
SEL1 Pulldown
SEL0 Pulldown
853S058 REVISION B 1/6/15
1 ©2015 Integrated Device Technology, Inc.

1 Page





853S058 pdf, ピン配列
Function Tables
Table 3. Control Input Function Table
Inputs
SEL2
SEL1
0 (default)
0
00
01
01
10
10
11
11
SEL0
0
1
0
1
0
1
0
1
Outputs
Q nQ
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
PCLK4
nPCLK4
PCLK5
nPCLK5
PCLK6
nPCLK6
PCLK7
nPCLK7
853S058 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
Outputs, IO
Continuous Current
Surge Current
Operating Temperature Range, TA
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
4.6V (LVPECL mode, VEE = 0V)
-4.6V (ECL mode, VCC = 0V)
-0.5V to VCC + 0.5V
0.5V to VEE – 0.5V
50mA
100mA
-40C to +85C
85.1C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.465V; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VCC Positive Supply Voltage
IEE Power Supply Current
2.375
3.3
Maximum
3.465
55
Units
V
mA
REVISION B 1/6/15
3 8:1 DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL
CLOCK MULTIPLEXER


3Pages


853S058 電子部品, 半導体
853S058 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.075ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "Rohde & Schwarz SMA100A Signal
Generator 9kHz - 6GHz as external input to an Agilent 8133A 3GHz
Pulse Generator".
8:1 DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL
CLOCK MULTIPLEXER
6
REVISION B 1/6/15

6 Page



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部品番号部品説明メーカ
853S058

LVPECL/ECL Clock Multiplexer

IDT
IDT


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