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853S011BのメーカーはIDTです、この部品の機能は「LVPECL/ ECL Fanout Buffer」です。 |
部品番号 | 853S011B |
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部品説明 | LVPECL/ ECL Fanout Buffer | ||
メーカ | IDT | ||
ロゴ | |||
このページの下部にプレビューと853S011Bダウンロード(pdfファイル)リンクがあります。 Total 20 pages
Low Skew, 1-to-2, Differential-to-2.5V, 3.3V
LVPECL/ ECL Fanout Buffer
853S011B
Datasheet
General Description
The 853S011B is a low skew, high performance 1-to-2
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
853S011B is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the 853S011B ideal for those clock distribution
applications demanding well defined performance and repeatability.
Features
• Two differential 2.5V, 3.3V LVPECL/ECL outputs
• One differential PCLK, nPCLK input pair
• PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >2.5GHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
• Output skew: 5ps (typical)
• Part-to-part skew: 130ps (maximum)
• Propagation delay: 355ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
Block Diagram
PCLK Pulldown
nPCLK Pullup/Pulldown
Q0
nQ0
Q1
nQ1
©2016 Integrated Device Technology, Inc.
Pin Assignment
Q0 1
nQ0 2
Q1 3
nQ1 4
8 VCC
7 PCLK
6 nPCLK
5 VEE
853S011B
8-Lead SOIC, 150MIL
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
8-Lead TSSOP, 118MIL
3.0mm x 3.0mm x 0.97mm package body
G Package
Top View
1 Revision B, February 23, 2016
1 Page 853S011B Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
Outputs, IO
Continuous Current
Surge Current
Operating Temperature Range, TA
Package Thermal Impedance, JA
(Junction-to-Ambient) for 8 Lead SOIC
Package Thermal Impedance, JA
(Junction-to-Ambient) for 8 Lead TSSOP
Storage Temperature, TSTG
Rating
4.6V (LVPECL mode, VEE = 0V)
-4.6V (ECL mode, VCC = 0V)
-0.5V to VCC + 0.5V
0.5V to VEE – 0.5V
50mA
100mA
-40C to +85C
102C/W (0 mps)
145.4C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = VCCO = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VCC Positive Supply Voltage
IEE Power Supply Current
2.375
3.3
3.8
25
Units
V
mA
©2016 Integrated Device Technology, Inc.
3
Revision B, February 23, 2016
3Pages 853S011B Datasheet
AC Electrical Characteristics
Table 4. AC Characteristics, VCC = -3.8V to -2.375V or , VCC = VCCO = 2.375V to 3.8V; VEE = 0V,
TA = -40°C to 85°C
-40°C
25°C
Symbol Parameter
Min Typ Max Min Typ Max Min
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
>2.5
>2.5
195 330 210 340 215
5 20
5 20 5
tsk(pp) Part-to-Part Skew; NOTE 3, 4
130 130
Buffer Additive Phase Jitter,
tjit RMS; refer to Additive Phase
Jitter Section
0.026
0.026
tR / tF
Output
Rise/Fall Time
20% to 80%
70
250 80
250 90
odc Output Duty Cycle; f 750MHz 48 50 52 48 50 52 48
85°C
Typ
0.026
50
Max
>2.5
355
20
130
250
52
Units
GHz
ps
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters are measured at f 1.7GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc.
6
Revision B, February 23, 2016
6 Page | |||
ページ | 合計 : 20 ページ | ||
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PDF ダウンロード | [ 853S011B データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
853S011B | LVPECL/ ECL Fanout Buffer | IDT |