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8413S12B の電気的特性と機能

8413S12BのメーカーはIDTです、この部品の機能は「HCSL/ LVCMOS Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 8413S12B
部品説明 HCSL/ LVCMOS Clock Generator
メーカ IDT
ロゴ IDT ロゴ 




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8413S12B Datasheet, 8413S12B PDF,ピン配置, 機能
HCSL/ LVCMOS Clock Generator
8413S12B
General Description
The 8413S12B is a PLL-based clock generator. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express, sRIO, XAUI, SerDes reference
clocks and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs.
The output frequencies are generated from a 25MHz external input
source or an external 25MHz parallel resonant crystal. The industrial
temperature range of the 8413S12B supports telecommunication,
networking, and storage requirements.
Applications
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
Pin Assignment
Features
Ten selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
clocks for PCI Express, sRIO and GbE, HCSL interface levels
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15output impedance
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
GND
FSEL_A0
FSEL_A1
FSEL_B0
FSEL_B1
FSEL_C0
FSEL_C1
FSEL_D0
FSEL_D1
FSEL_E0
VDDA
FSEL_E1
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1 54
2 53
3 52
4 51
5 50
6 ;;;;;;
7
49
48
8 47
9
10
6
46
45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
nc
VDD
IREF
OE_D
nQD1
QD1
nQD0
QD0
VDDO_D
VDDO_C
nQC1
QC1
nQC0
QC0
OE_C
VDD
GND
nc
SLQPP[PP/4)33DFNDJH
©2016 Integrated Device Technology, Inc.
1
Revision E, August 18, 2016

1 Page





8413S12B pdf, ピン配列
8413S12B Datasheet.
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 18, 38
2,
3
4,
5
6,
7
8,
9
10,
12
11
13, 16, 19,
36, 37, 54,
55, 72
14,
15
Name
GND
FSEL_A0.
FSEL_A1
FSEL_B0,
FSEL_B1
FSEL_C0,
FSEL_C1
FSEL_D0,
FSEL_D1
FSEL_E0,
FSEL_E1
VDDA
nc
XTAL_IN,
XTAL_OUT
Type
Power
Input
Pulldown
Input
Pulldown
Input
Pulldown
Input
Pulldown
Input
Power
Pulldown
Description
Power supply ground.
Selects the QAx, nQAx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QBx, nQBx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QCx, nQCx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QDx, nQDx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QEx, nQEx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Unused
No connect.
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
17
20, 39, 53
21
REF_SEL
VDD
PLL_SEL
Input
Power
Input
Pullup
Pullup
Input source control pin. See Table 3C. LVCMOS/LVTTL interface levels.
Core supply pins.
PLL bypass control pin. See Table 3B. LVCMOS/LVTTL interface levels.
22
CLK
Input
Pulldown Non-inverting differential clock input.
23
24
25
26, 27
28, 29
30
31, 32
33, 34
35
40
nCLK
OE_A
VDDO_A
QA0, nQA0
QA1, nQA1
OE_B
QB0, nQB0
QB1, nQB1
VDDO_B
OE_C
Input
Input
Power
Output
Output
Input
Output
Output
Power
Input
Pullup/
Pulldown
Pullup
Pullup
Pullup
Inverting differential clock input. Internal resistor bias to VDD/2.
Active HIGH output enable for Bank A outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Bank A (HCSL) output supply pin. 3.3 V supply.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Active HIGH output enable for Bank B outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Bank B (HCSL) output supply pin. 3.3V supply.
Active HIGH output enable for Bank C outputs. See Table 3D.
LVCMOS/LVTTL interface levels.
41, 42
QC0, nQC0
Output
Differential output pair. HCSL interface levels.
43, 44
QC1, nQC1
Output
Differential output pair. HCSL interface levels.
45
46
47, 48
VDDO_C
VDDO_D
QD0, nQD0
Power
Power
Output
Bank C (HCSL) output supply pin. 3.3V supply.
Bank D (HCSL) output and HCSL reference circuit supply pin. Must be
connected to 3.3V to use any of the HCSL outputs.
Differential output pair. HCSL interface levels.
49, 50
QD1, nQD1
Output
Differential output pair. HCSL interface levels.
©2016 Integrated Device Technology, Inc.
3
Revision E, August 18, 2016


3Pages


8413S12B 電子部品, 半導体
8413S12B Datasheet.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
XTAL_IN
Other Inputs
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
4.6V
0V to VDD
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
25.4°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_[F:G] = VDDO_QREF = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VDD
VDDA
VDDO_X
IDD
IDDA
IDDO_X
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
VDD – 0.16
3.135
No Load, CLK selected
NOTE: VDDO_X denotes VDDO_[A:E], VDDO_[F:G}, VDDO_QREF.
NOTE: IDDO_X denotes IDDO_[A:E] + IDDO_[F:G] + IDDO_QREF
Typical
3.3
3.3
3.3
86
13
76
Maximum
3.465
VDD
3.465
103
16
91
Units
V
V
V
mA
mA
mA
Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
VDDA
VDDO_X
IDD
IDDA
IDDO_X
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load, CLK selected
3.135
VDD – 0.16
2.375
3.3
3.3
2.5
79
13
50
3.465
VDD
2.625
95
16
60
V
V
V
mA
mA
mA
NOTE: VDDO_X denotes VDDO_G, VDDO_QREF.
NOTE: IDDO_X denotes IDDO_G + IDDO_QREF.
©2016 Integrated Device Technology, Inc
6
Revision E, August 18, 2016

6 Page



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共有リンク

Link :


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