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AD7156 の電気的特性と機能

AD7156のメーカーはAnalog Devicesです、この部品の機能は「2-Channel Capacitance Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD7156
部品説明 2-Channel Capacitance Converter
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD7156 Datasheet, AD7156 PDF,ピン配置, 機能
Ultralow Power, 1.8 V, 3 mm × 3 mm,
2-Channel Capacitance Converter
AD7156
FEATURES
Ultralow power
Power supply voltage: 1.8 V to 3.6 V
Operation power supply current: 70 μA typical
Power-down current: 2 μA typical
Fast response time
Conversion time: 10 ms per channel
Wake-up time from serial interface: 300 μs
Adaptive environmental compensation
2 capacitance input channels
Sensor capacitance (CSENS): 0 pF up to 13 pF
Sensitivity up to 3 fF
2 modes of operation
Standalone with fixed settings
Interfaced to a microcontroller for user-defined settings
2 detection output flags
2-wire serial interface (I2C-compatible)
Operating temperature: −40°C to +85°C
10-lead LFCSP package (3 mm × 3 mm × 0.8 mm)
APPLICATIONS
Buttons and switches
Proximity sensing
Contactless switching
Position detection
Level detection
Portable products
GENERAL DESCRIPTION
The AD7156 delivers a complete signal processing solution for
capacitive sensors, featuring an ultralow power converter with
fast response time.
The AD7156 uses an Analog Devices, Inc., capacitance-to-
digital converter (CDC) technology, which combines features
important for interfacing to real sensors, such as high input
sensitivity and high tolerance of both input parasitic ground
capacitance and leakage current.
The integrated adaptive threshold algorithm compensates for
any variations in the sensor capacitance due to environmental
factors like humidity and temperature or due to changes in the
dielectric material over time.
By default, the AD7156 operates in standalone mode using the
fixed power-up settings and indicates detection on two digital
outputs. Alternatively, the AD7156 can be interfaced to a micro-
controller via the serial interface, the internal registers can be
programmed with user-defined settings, and the data and status
can be read from the part.
The AD7156 operates with a 1.8 V to 3.6 V power supply. It is
specified over the temperature range of −40°C to +85°C.
CSENS1
CSENS2
CIN1
EXC1
CIN2
EXC2
FUNCTIONAL BLOCK DIAGRAM
VDD
Σ-Δ CDC
MUX AD7156
DIGITAL
FILTER
THRESHOLD
SERIAL
INTERFACE
EXCITATION
THRESHOLD
GND
Figure 1.
SCL
SDA
OUT1
OUT2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.

1 Page





AD7156 pdf, ピン配列
AD7156
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Capacitance-to-Digital Converter............................................ 11
CAPDAC ..................................................................................... 11
Comparator and Threshold Modes.......................................... 12
Adaptive Threshold.................................................................... 12
Sensitivity..................................................................................... 12
Data Average ............................................................................... 13
Hysteresis..................................................................................... 13
Timeout........................................................................................ 13
Auto-DAC Adjustment.............................................................. 14
Power-Down Timer ................................................................... 14
Register Descriptions ..................................................................... 15
Status Register ............................................................................. 16
Data Registers ............................................................................. 17
Average Registers........................................................................ 18
REVISION HISTORY
10/08—Revision 0: Initial Version
Fixed Threshold Registers ......................................................... 18
Sensitivity Registers ................................................................... 18
Timeout Registers....................................................................... 18
Setup Registers............................................................................ 19
Configuration Register .............................................................. 20
Power-Down Timer Register .................................................... 21
CAPDAC Registers .................................................................... 21
Serial Number Register.............................................................. 21
Chip ID Register......................................................................... 21
Serial Interface ................................................................................ 22
Read Operation........................................................................... 22
Write Operation.......................................................................... 22
AD7156 Reset ............................................................................. 23
General Call ................................................................................ 23
Hardware Design Considerations ................................................ 24
Overview ..................................................................................... 24
Parasitic Capacitance to Ground.............................................. 24
Parasitic Resistance to Ground................................................. 24
Parasitic Parallel Resistance ...................................................... 24
Parasitic Serial Resistance ......................................................... 25
Input Overvoltage Protection ................................................... 25
Input EMC Protection ............................................................... 25
Power Supply Decoupling and Filtering.................................. 25
Application Examples ................................................................ 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
Rev. 0 | Page 2 of 28


3Pages


AD7156 電子部品, 半導体
AD7156
TIMING SPECIFICATIONS
VDD = 1.8 V to 3.6 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, temperature range = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Min Typ Max Unit Test Conditions/Comments
CONVERTER
Conversion Time1
20 ms Both channels, 10 ms per channel.
Wake-Up Time from Power-Down Mode2, 3
0.3 ms
Power-Up Time2, 4
2 ms
Reset Time2, 5
2 ms
SERIAL INTERFACE6, 7
See Figure 2.
SCL Frequency
0 400 kHz
SCL High Pulse Width, tHIGH
0.6 μs
SCL Low Pulse Width, tLOW
1.3 μs
SCL, SDA Rise Time, tR
0.3 μs
SCL, SDA Fall Time, tF
0.3 μs
Hold Time (Start Condition), tHD;STA
0.6 μs After this period, the first clock is generated.
Setup Time (Start Condition), tSU;STA
0.6 μs Relevant for repeated start condition.
Data Setup Time, tSU;DAT
0.1 μs
Setup Time (Stop Condition), tSU;STO
0.6 μs
Data Hold Time (Master), tHD;DAT
10 ns
Bus-Free Time (Between Stop and Start Conditions), tBUF 1.3
μs
1 Conversion time is 304 internal clock cycles for both channels (nominal clock 16 kHz); the internal clock frequency is equal to the specified excitation frequency.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
4 Power-up time is the maximum delay between the VDD crossing the minimum level (1.8 V) and either the start of conversion or when ready to receive a serial
interface command.
5 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial
interface command.
6 Sample tested during initial release to ensure compliance.
7 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
SCL
tLOW tR
tHD;STA
tHD;DAT
SDA
tBUF
PS
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
S
Figure 2. Serial Interface Timing Diagram
tSU;STO
P
Rev. 0 | Page 5 of 28

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