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9DBV0441 の電気的特性と機能

9DBV0441のメーカーはIDTです、この部品の機能は「4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DBV0441
部品説明 4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
メーカ IDT
ロゴ IDT ロゴ 




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9DBV0441 Datasheet, 9DBV0441 PDF,ピン配置, 機能
4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohm
9DBV0441
DATASHEET
Description
The 9DBV0441 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It has integrated output
terminations providing Zo=100ohms for direct connection to
100ohm transmission lines. The device has 4 output enables
for clock management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 – 1-200Hz Low-Power (LP) HCSL DIF pairs w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for 12kHz-20MHz
Block Diagram
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard HCSL outputs
53mW typical power consumption in PLL mode; minimal
power consumption
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(3:0)#
CLK_IN
CLK_IN#
^SADR_tri
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
ZDB PLL
DIF3
DIF2
DIF1
DIF0
9DBV0441 REVISION E 04/28/16 1 ©2016 Integrated Device Technology, Inc.

1 Page





9DBV0441 pdf, ピン配列
Power Connections
Pin Number
VDD
GND
47
98
16, 25
15,20,26,30
21 20
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
Frequency Select Table
FSEL
Byte3 [4:3]
00 (Default)
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
9DBV0441 DATASHEET
REVISION E 04/28/16
3 4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM


3Pages


9DBV0441 電子部品, 半導体
9DBV0441 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0441. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Applies to all VDD pins
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Input High Voltage - DIF_IN VIHDIF
Input Low Voltage - DIF_IN
Input Common Mode
Voltage - DIF_IN
VILDIF
VCOM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
600 800
VSS - 300
0
300
1150
mV
1
300 mV 1,3
725 mV 1
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Peak to Peak value (VIHDIF - VILDIF)
Measured differentially
300
0.4
1450
mV
V/ns
1
1,2
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
5 uA 1
55 % 1
150 ps 1
3 The device can be driven from a single ended clock by driving the true clock and biasing the complement clock input to the VBIAS, where VBIAS
is (VIHHIGH - VIHLOW)/2
4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM
6
REVISION E 04/28/16

6 Page



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部品番号部品説明メーカ
9DBV0441

4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB

IDT
IDT


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