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9DBV0431 の電気的特性と機能

9DBV0431のメーカーはIDTです、この部品の機能は「4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DBV0431
部品説明 4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer
メーカ IDT
ロゴ IDT ロゴ 




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9DBV0431 Datasheet, 9DBV0431 PDF,ピン配置, 機能
4-output 1.8V PCIe Gen1-2-3
Zero-delay/Fanout Buffer (ZDB/FOB)
9DBV0431
DATASHEET
Description
The 9DBV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 - 1-200Hz Low-Power (LP) HCSL DIF pairs
w/ZO=100ohms
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs save 8 resistors; minimal board space
and BOM cost
53mW typical power consumption in PLL mode; minimal
power consumption
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(3:0)#
4
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF3
DIF2
DIF1
DIF0
9DBV0431 REVISION E 04/28/16 1 ©2016 Integrated Device Technology, Inc.

1 Page





9DBV0431 pdf, ピン配列
9DBV0431 DATASHEET
Pin Descriptions
Pin# Pin Name
Type Pin Description
1
^vHIBW_BYPM_LOB
LATCHED
IN
Trilevel input to select High BW, Bypass or Low
See PLL Operating Mode Table for Details.
BW mode.
2 FB_DNC
DNC
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
3 FB_DNC#
DNC
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
4 VDDR1.8
PWR
1.8V power for differential input clock (receiver). This VDD should be treated as an
Analog power rail and filtered appropriately.
5 CLK_IN
IN True Input for differential reference clock.
6 CLK_IN#
IN Complementary Input for differential reference clock.
7 GNDR
GND Analog Ground pin for the differential input (receiver)
8 GNDDIG
GND Ground pin for digital circuitry
9 VDDDIG1.8
PWR 1.8V digital power (dirty power)
10 SCLK_3.3
IN Clock pin of SMBus circuitry, 3.3V tolerant.
11 SDATA_3.3
I/O Data pin for SMBus circuitry, 3.3V tolerant.
12 vOE0#
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
13 DIF0
OUT Differential true clock output
14 DIF0#
OUT Differential Complementary clock output
15 GND
GND Ground pin.
16 VDDO1.8
PWR Power supply for outputs, nominally 1.8V.
17 vOE1#
IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18 DIF1
OUT Differential true clock output
19 DIF1#
OUT Differential Complementary clock output
20 GNDA
GND Ground pin for the PLL core.
21 VDDA1.8
PWR 1.8V power for the PLL core.
22 DIF2
OUT Differential true clock output
23 DIF2#
OUT Differential Complementary clock output
24 vOE2#
IN Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
25 VDDO1.8
PWR Power supply for outputs, nominally 1.8V.
26 GND
GND Ground pin.
27 DIF3
OUT Differential true clock output
28 DIF3#
OUT Differential Complementary clock output
29 vOE3#
IN Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
30 GND
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
31 ^CKPWRGD_PD#
IN Low enters Power Down Mode, subsequent high assertions exit Power Down Mode.
This pin has internal pull-up resistor.
32 ^SADR_tri
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
33 ePad
GND Connect epad to ground.
REVISION E 04/28/16
3 4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)


3Pages


9DBV0431 電子部品, 半導体
9DBV0431 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
MAX UNITS NOTES
1.8V Supply Voltage
VDD
Supply voltage for core, analog and LVCMOS
outputs
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
Input SS Modulation
Frequency
OE# Latency
Tdrive_PD#
TCOM
TIND
VIH
VIM
VIL
IIN
IINP
Fibyp
Fipll100
Fipll125
Fipll62
Lpin
CIN
CINDIF_IN
COUT
TSTAB
fMODIN
tLATOE#
tDRVPD
Commmercial range
Industrial range
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
125MHz PLL mode
50MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating Frequency fMAXSMB
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.25VDDSMB
5 For VDDSMB < 3.3V, VIHSMB >= 0.7VDDSMB
6DIF_IN input
7The differential input clock must be running for the SMBus to be active
1.7
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
-200
1
50
62.5
25
1.5
1.5
30
1
2.1
4
1.7
1.8 1.9 V
25 70 °C
25 85 °C
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
V
V
uA
200 uA
200 MHz
100 140 MHz
125 175 MHz
50 65 MHz
7 nH
5 pF
2.7 pF
6 pF
0.6 1 ms
31.5
175
33 kHz
3 clocks
300
5
5
0.8
3.6
0.4
3.6
1000
300
400
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1,6
1
1,2
1
1,3
1,3
1,2
1,2
1,4
1,5
1
1
1
1
1
1,7
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 6
REVISION E 04/28/16

6 Page



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部品番号部品説明メーカ
9DBV0431

4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer

IDT
IDT


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