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9DBL04 の電気的特性と機能

9DBL04のメーカーはIDTです、この部品の機能は「4-output 3.3V PCIe Zero-delay Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DBL04
部品説明 4-output 3.3V PCIe Zero-delay Buffer
メーカ IDT
ロゴ IDT ロゴ 




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9DBL04 Datasheet, 9DBL04 PDF,ピン配置, 機能
4-output 3.3V PCIe Zero-delay Buffer
9DBL04
Description
The 9DBL04 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DBL04 supports PCIe
Gen1-4 Common Clocked (CC) and PCIe Separate
Reference Independent Spread (SRIS) systems. It offers a
choice of integrated output terminations providing direct
connection to 85or 100transmission lines. The
9DBL04P2 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
4 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0442 default ZOUT = 100
9DBL0452 default ZOUT = 85
9DBL04P2 factory programmable defaults
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2-3 SRIS in fan-out mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Block Diagram
DATASHEET
Features/Benefits
Direct connection to 100(xx42) or 85(xx52)
transmission lines; saves 16 resistors compared to
standard PCIe devices
132mW typical power consumption in PLL mode;
eliminates thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
Customer defined SMBus power up default can be
programmed into P2 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Note: Resistors default to internal on xx42/xx52 devices. P2 devices have programmable default impedances on an output-by-output basis.
9DBL04 NOVEMBER 11, 2016
1 ©2016 Integrated Device Technology, Inc.

1 Page





9DBL04 pdf, ピン配列
9DBL04 DATASHEET
Pin Descriptions
Pin# Pin Name
Type Pin Description
LATCHED Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2
1 ^vHIBW_BYPM_LOB IN (Bypass mode) with internal pull up/pull down resistors. See PLL Operating Mode Table for
Details.
2 FB_DNC
DNC
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
3 FB_DNC#
DNC
Complement clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
4 VDDR3.3
PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
5 CLK_IN
IN True Input for differential reference clock.
6 CLK_IN#
IN Complementary Input for differential reference clock.
7 NC
N/A No Connection.
8 GNDDIG
GND Ground pin for digital circuitry
9 SCLK_3.3
IN Clock pin of SMBus circuitry, 3.3V tolerant.
10 SDATA_3.3
I/O Data pin for SMBus circuitry, 3.3V tolerant.
11 VDDDIG3.3
PWR 3.3V digital power (dirty power)
12 vOE0#
IN Active low input for enabling output 0. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
13 DIF0
OUT Differential true clock output
14 DIF0#
OUT Differential Complementary clock output
15 VDDO3.3
PWR Power supply for outputs,nominal 3.3V.
16 NC
N/A No Connection.
17 DIF1
OUT Differential true clock output
18 DIF1#
OUT Differential Complementary clock output
19 vOE1#
IN Active low input for enabling output 1. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
20 NC
N/A No Connection.
21 VDDA3.3
PWR 3.3V power for the PLL core.
22 DIF2
OUT Differential true clock output
23 DIF2#
OUT Differential Complementary clock output
24 vOE2#
IN
Active low input for enabling output 2. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
25 VDDO3.3
PWR Power supply for outputs,nominal 3.3V.
26 NC
N/A No Connection.
27 DIF3
OUT Differential true clock output
28 DIF3#
OUT Differential Complementary clock output
29 vOE3#
IN Active low input for enabling output 3. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
30 NC
N/A No Connection.
Input notifies device to sample latched inputs and start up on first high assertion. Low
31 ^CKPWRGD_PD#
IN enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal 120kohm pull-up resistor.
32 vSADR_tri
LATCHED Tri-level latch to select SMBus Address. It has an internal 120kohm pull down resistor.
IN See SMBus Address Selection Table.
33 epad
GND connect epad to ground.
NOTE: DNC indicates Do Not Connect anything to this pin.
NOVEMBER 11, 2016
3 4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER


3Pages


9DBL04 電子部品, 半導体
9DBL04 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
Ambient Operating
Temperature
VDDx
TAMB
Supply voltage for core and analog
Industrial range
3.135 3.3 3.465 V
-40 25 85 °C
Input High Voltage
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
VIH
VIL
VIHtri
VIMtri
VILtri
IIN
IINP
FIN
Lpin
CIN
CINDIF_IN
COUT
TSTAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
50MHz PLL mode
125MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.75 VDDx
VDDx + 0.3
-0.3
0.75 VDDx
0.4 VDDx
-0.3
-5
0.5 VDDx
0.25 VDDx
VDD + 0.3
0.6 VDDx
0.25 VDDx
5
-50 50
1 200
60 100.00 140
30 50.00 65
75 125.00 175
7
1.5 5
1.5 2.7
6
1
V
V
V
V
V
uA
uA
MHz
MHz
MHz
MHz
nH
pF
pF
pF
ms
2
2
2
2
1
1
1
1
1,2
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30
33 kHz
Input SS Modulation
Frequency non-PCIe
fMODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall tF Fall time of single-ended control inputs
Trise
tR Rise time of single-ended control inputs
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
0
1
66 kHz
3 clocks 1,3
300 us 1,3
5 ns 2
5 ns 2
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
6
NOVEMBER 11, 2016

6 Page



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