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9DBV0641 の電気的特性と機能

9DBV0641のメーカーはIDTです、この部品の機能は「6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DBV0641
部品説明 6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
メーカ IDT
ロゴ IDT ロゴ 




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9DBV0641 Datasheet, 9DBV0641 PDF,ピン配置, 機能
6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBV0641
DATASHEET
Description
The 9DBV0641 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF additive phase jitter <300fs rms for SGMII
Block Diagram
Features/Benefits
Direct connection to 100ohm transmission lines; saves 24
resistors compared to standard PCIe devices
55mW typical power consumption in PLL mode; minimal
power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(5:0)#
6
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0641 REVISION B 09/11/14 1 ©2014 Integrated Device Technology, Inc.

1 Page





9DBV0641 pdf, ピン配列
Power Connections
Pin Number
VDD
VDDIO
5
11
16, 31
25
12,17,26,32,
39
GND
41
8
41
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
PLL Analog
Frequency Select Table
FSEL
Byte3 [1:0]
00
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
9DBV0641 DATASHEET
REVISION B 09/11/14
3 6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS


3Pages


9DBV0641 電子部品, 半導体
9DBV0641 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0641. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5
3.6
150
125
UNITS NOTES
V 1,2
V 1,3
V1
°C 1
°C 1
V1
Electrical Characteristics–Clock Input Parameters
TA = TAMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage - DIF_IN VIHDIF
Input Low Voltage - DIF_IN
Input Common Mode
Voltage - DIF_IN
VILDIF
VCOM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
300 750
VSS - 300
200
0
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Peak to Peak value (VIHDIF - VILDIF)
Measured differentially
300
0.35
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
MAX
1150
300
725
1450
8
5
55
150
UNITS NOTES
mV 1
mV 1
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
6
REVISION B 09/11/14

6 Page



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部品番号部品説明メーカ
9DBV0641

6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB

IDT
IDT


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