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9DBU0841 の電気的特性と機能

9DBU0841のメーカーはIDTです、この部品の機能は「8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DBU0841
部品説明 8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
メーカ IDT
ロゴ IDT ロゴ 




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9DBU0841 Datasheet, 9DBU0841 PDF,ピン配置, 機能
8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBU0841
DATASHEET
Description
The 9DBU0841 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated output terminations
providing Zo=100for direct connection to 100
transmission lines. The device has 8 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
8 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 80ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Very low additive phase jitter in bypass mode
Block Diagram
Features/Benefits
Direct connection to 100transmission lines; saves 32
resistors compared to standard HCSL outputs
53mW typical power consumption in PLL mode; eliminates
thermal concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
8
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0841 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.

1 Page





9DBU0841 pdf, ピン配列
9DBU0841 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
1 vSADR_tri
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
2 ^vHIBW_BYPM_LOBW# LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
IN See PLL Operating Mode Table for Details.
3 FB_DNC
DNC
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
4 FB_DNC#
DNC
Complement clock of differential feedback. The feedback output and feedback
input are connected internally on this pin. Do not connect anything to this pin.
5 VDDR1.5
6 CLK_IN
7 CLK_IN#
8 GNDR
9 GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG1.5
13 VDDIO
14 vOE0#
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
20 VDD1.5
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
26 DIF3
27 DIF3#
28 vOE3#
29 GNDA
30 VDDA1.5
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
37 vOE5#
38 VDD1.5
39 VDDIO
40 GND
PWR
IN
IN
GND
GND
IN
I/O
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
GND
OUT
OUT
IN
OUT
OUT
IN
GND
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
GND
1.5V power for differential input clock (receiver). This VDD should be treated as
an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.5V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominally 1.5V
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
1.5V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominally 1.5V
Power supply for differential outputs
Ground pin.
REVISION C 04/22/15
3 8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS


3Pages


9DBU0841 電子部品, 半導体
9DBU0841 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
Output Supply Voltage
VDDIO
Supply voltage for Low Power HCSL Outputs
Ambient Operating
Temperature
TAMB
Commmercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
VIH
VIM
VIL
IIN
IINP
Fibyp
Fipll
Lpin
CIN
CINDIF_IN
COUT
TSTAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Input SS Modulation
Frequency non-PCIe
fMODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
Bus Voltage
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
5DIF_IN input
6The differential input clock must be running for the SMBus to be active
1.425
0.95
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
1.5
1.05-1.5
25
25
1.575
1.575
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
V
°C
°C
V
V
V
uA
-200 200 uA
1 167 MHz
20
100.00 110
MHz
7 nH
1.5 5 pF
1.5 2.7 pF
6 pF
1 ms
30
0
1
2.1
4
1.425
33 kHz
66 kHz
3 clocks
300
5
5
0.6
3.3
0.4
3.3
1000
300
400
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1
1
2
2
1
1
1,5
1
1,2
1,3
1,3
2
2
4
1
1
6
8 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
6
REVISION C 04/22/15

6 Page



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部品番号部品説明メーカ
9DBU0841

8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB

IDT
IDT


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