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9DBU0241のメーカーはIDTです、この部品の機能は「2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB」です。 |
部品番号 | 9DBU0241 |
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部品説明 | 2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB | ||
メーカ | IDT | ||
ロゴ | |||
このページの下部にプレビューと9DBU0241ダウンロード(pdfファイル)リンクがあります。 Total 17 pages
2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBU0241
DATASHEET
Description
The 9DBU0241 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 2 output enables for clock
management.
Recommended Application
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
• 2 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
• DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
• Direct connection to 100 transmission lines; saves 8
resistors compared to standard HCSL outputs
• 35mW typical power consumption in PLL mode; eliminates
thermal concerns
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
9DBU0241 REVISION C 04/22/15 1 ©2015 Integrated Device Technology, Inc.
1 Page 9DBU0241 DATASHEET
Pin Descriptions
Pin#
Pin Name
Pin Type
Description
Complement clock of differential feedback. The feedback output
1 FB_DNC#
DNC and feedback input are connected internally on this pin. Do not
connect anything to this pin.
2 VDDR1.5
PWR
1.5V power for differential input clock (receiver). This VDD should
be treated as an Analog power rail and filtered appropriately.
3 CLK_IN
IN True Input for differential reference clock.
4 CLK_IN#
IN Complementary Input for differential reference clock.
5 GNDR
GND Analog Ground pin for the differential input (receiver)
6 GNDDIG
GND Ground pin for digital circuitry
7 VDDDIG1.5
PWR 1.5V digital power (dirty power)
8 SCLK_3.3
IN Clock pin of SMBus circuitry, 3.3V tolerant.
9 SDATA_3.3
I/O Data pin for SMBus circuitry, 3.3V tolerant.
10 GND
GND Ground pin.
11 VDDO1.5
PWR Power supply for outputs, nominally 1.5V.
Active low input for enabling DIF pair 0. This pin has an internal pull-
12 vOE0#
IN down.
1 =disable outputs, 0 = enable outputs
13 DIF0
OUT Differential true clock output
14 DIF0#
OUT Differential Complementary clock output
15 GNDA
GND Ground pin for the PLL core.
16 VDDA1.5
PWR 1.5V power for the PLL core.
17 DIF1
OUT Differential true clock output
18 DIF1#
OUT Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-
19 vOE1#
IN down.
1 =disable outputs, 0 = enable outputs
20 VDDO1.5
PWR Power supply for outputs, nominally 1.5V.
21 GND
GND Ground pin.
Input notifies device to sample latched inputs and start up on first
22 ^CKPWRGD_PD#
IN
high assertion. Low enters Power Down Mode, subsequent high
assertions exit Power Down Mode. This pin has internal pull-up
resistor.
23 ^vHIBW_BYPM_LOBW# LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
IN See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and
24 FB_DNC
DNC feedback input are connected internally on this pin. Do not connect
anything to this pin.
25 ePad
GND Connect epad to ground.
NOTE: DNC indicates Do Not Connect anything to this pin.
REVISION C 04/22/15
3 2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
3Pages 9DBU0241 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Supply Voltage
VDDx
Supply voltage for core and analog
Ambient Operating
Temperature
TAMB
Commmercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
VIH
VIM
VIL
IIN
IINP
Fibyp
Fipll
Lpin
CIN
CINDIF_IN
COUT
TSTAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
Input SS Modulation
Frequency non-PCIe
fMODINPCIe
fMODIN
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
Tdrive_PD#
tLATOE#
tDRVPD
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
Bus Voltage
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
5DIF_IN input
6The differential input clock must be running for the SMBus to be active
1.425
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
-200
1
20
1.5
1.5
30
0
1
2.1
4
1.425
TYP
1.5
25
25
MAX UNITS NOTES
1.575
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
°C
°C
V
V
V
uA
1
1
200 uA
100.00
167
110
7
5
2.7
6
1
MHz
MHz
nH
pF
pF
pF
ms
2
2
1
1
1,5
1
1,2
33 kHz
66 kHz
3 clocks 1,3
300 us 1,3
5
5
0.6
3.3
0.4
3.3
1000
300
ns
ns
V
V
V
mA
V
ns
ns
2
2
4
1
1
400 kHz 6
2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
6
REVISION C 04/22/15
6 Page | |||
ページ | 合計 : 17 ページ | ||
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PDF ダウンロード | [ 9DBU0241 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
9DBU0241 | 2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB | IDT |