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9DB423B の電気的特性と機能

9DB423BのメーカーはIDTです、この部品の機能は「Four Output Differential Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DB423B
部品説明 Four Output Differential Buffer
メーカ IDT
ロゴ IDT ロゴ 




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9DB423B Datasheet, 9DB423B PDF,ピン配置, 機能
DATASHEET
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
9DB423B
Recommended Application:
DB400Q compatible part with PCIe Gen1, Gen 2 and QPI
support
General Description:
The ICS9DB423 is compatible with the Intel DB400Q Differential
Buffer Specification. This buffer provides 4 PCI-Express SRC or
4 QPI clocks. The ICS9DB423 is driven by a differential output
pair from a CK410B+ or CK509B main clock generator.
Key Specifications
• Output cycle-cycle jitter < 50ps.
• Output to Output skew <50ps
• Phase jitter: PCIe Gen1 < 86ps peak to peak
• Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
• Phase jitter: QPI < 0.5ps rms
• RoHS compliant packaging
Features/Benefits
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
• Supports undriven differential outputs in Power Down and
DIF_STOP# modes for power management.
Output Features
• 4 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
• 50-133 MHz operation in PLL mode
• 33-400 MHz operation in Bypass mode
Funtional Block Diagram
OE(6,1)
2
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
4
M
U
STOP
X LOGIC
DIF(6,5,2,1)
PD
BYPASS#_133_100
HIGH_BW#
DIF_STOP#
SDATA
SCLK
CONTROL
LOGIC
IREF
Note: Polarities shown for OE_INV = 0.
IDT® Four Output Differential Buffer for PCIe and Gen 1, Gen 2 and QPI
1
1437B - 02/04/10

1 Page





9DB423B pdf, ピン配列
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Pin Description for OE_INV = 0
PIN #
PIN NAME
1 VDD
2 SRC_IN
3 SRC_IN#
4 GND
5 VDD
6 DIF_1
7 DIF_1#
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
8 OE_1
IN
9 DIF_2
10 DIF_2#
11 VDD
OUT
OUT
PWR
12 BYPASS#_133_100
IN
13 SCLK
14 SDATA
IN
I/O
15 PD#
IN
16 DIF_STOP#
IN
17 HIGH_BW#
IN
18 VDD
19 DIF_5#
20 DIF_5
PWR
OUT
OUT
21 OE_6
IN
22 DIF_6#
23 DIF_6
24 VDD
OUT
OUT
PWR
25 OE_INV
IN
26 IREF
27 GNDA
28 VDDA
OUT
PWR
PWR
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out), QPI PLL (133MHz) or PCIe PLL (100MHz) mode
0 = Bypass mode, M= QPI, 1= PCIe PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
Active low input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
3
1437B - 02/04/10


3Pages


9DB423B 電子部品, 半導体
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Electrical Characteristics - Clock Input Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage - DIF_IN VIHDIF
Differential inputs
(single-ended measurement)
Input Low Voltage - DIF_IN VILDIF
Differential inputs
(single-ended measurement)
Input Common Mode Voltage -
DIF_IN
VCOM
Common Mode Input Voltage
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Peak to Peak value
Measured differentially
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle
dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through Vswing min centered around differential zero
MIN TYP
600 800
VSS - 300
300
300
0.4
-5
45
0
0
MAX
1150
UNITS NOTES
mV 1
300 mV 1
1000
1450
8
5
55
125
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
1
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
6
1437B - 02/04/10

6 Page



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部品番号部品説明メーカ
9DB423B

Four Output Differential Buffer

IDT
IDT


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