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9DB233 の電気的特性と機能

9DB233のメーカーはIDTです、この部品の機能は「Two Output Differential Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 9DB233
部品説明 Two Output Differential Buffer
メーカ IDT
ロゴ IDT ロゴ 




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9DB233 Datasheet, 9DB233 PDF,ピン配置, 機能
DATASHEET
Two Output Differential Buffer for PCIe Gen3
9DB233
Recommended Application:
2 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB233 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB233 suitable for Express Card
applications.
Features/Benefits:
• OE# pins/Suitable for Express Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input
clock for low EMI
• SMBus Interface/unused outputs can be disabled
Output Features:
• 2 - 0.7V current mode differential output pairs (HCSL)
Key Specifications:
• Cycle-to-cycle jitter < 50 ps
• Output-to-output skew < 50 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
Block Diagram
OE0#
OE1#
SRC_IN
SRC_IN#
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
DIF_0
DIF_1
IREF
IDT® Two Output Differential Buffer for PCIe Gen3
1
1667C—04/20/11

1 Page





9DB233 pdf, ピン配列
9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
Pin Description
PIN # PIN NAME PIN TYPE
DESC RIPTION
1 PLL_BW IN
2 SRC_IN IN
3 SRC_IN# IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
4 vOE0# IN
Activ e low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
5 VDD
PWR
6 GND
PWR
7 DIF_0
OU T
8 DIF_0# OUT
9 VDD
PWR
10 SMBDAT I/O
11 SMBCLK IN
12 VDD
PWR
13 DIF_1# OUT
14 DIF_1
OU T
15 GND
PWR
16 VDD
PWR
17 vOE1# IN
18 IREF
OU T
19 GNDA
20 VDDA
PWR
PWR
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Data pin of SMBUS c ircuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
Activ e low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT® Two Output Differential Buffer for PCIe Gen3
3
1667C—04/20/11


3Pages


9DB233 電子部品, 半導体
9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
PLL Bandwidth
PLL Jitter Peaking
Duty Cycle
BW
tJPEAK
tDC
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
2 2.3
0.4 0.5
1
45 48
MAX
4
1
2
55
UNITS NOTES
MHz
MHz
dB
1
1
1
%1
Duty Cycle Distortion
tDCD Measured differentially, Bypass Mode @100MHz -2
1
2 % 1,4
Skew, Input to Output
tpdBYP
tpdPLL
Bypass Mode, VT = 50%
Hi BW PLL Mode VT = 50%
2500
-250
3660
0
4500
250
ps
ps
1
1
Skew, Output to Output
tsk3
VT = 50%
15 50 ps 1
Jitter, Cycle to cycle
tjcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
40 50 ps 1,3
10 50 ps 1,3
1Guaranteed by design and characterization, not 100% tested in production.
2 IREF = VDD/(3xRR). For RR = 475(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
3 Measured from differential waveform
4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
Electrical Characteristics - PCIe Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
tjphPCIeG1
PCIe Gen 1
PCIe Gen 2 Lo Band
Phase Jitter, PLL Mode
tjphPCIeG2
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
MIN
TYP
MAX
32 86
1.1 3
2.3 3.1
0.5 1
tjphPCIeG1
PCIe Gen 1
25
Additive Phase Jitter,
Bypass Mode
tjphPCIeG2
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.2
0.8
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.1
1 Applies to all outputs.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Subject to final radification by PCI SIG.
0.3
1
0.2
UNITS
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
Notes
1,2,3
1,2
1,2
1,2,4
ps (p-p) 1,2,3
ps
(rms)
ps
(rms)
ps
(rms)
1,2
1,2
1,2,4
IDT® Two Output Differential Buffer for PCIe Gen3
6
1667C—04/20/11

6 Page



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部品番号部品説明メーカ
9DB233

Two Output Differential Buffer

IDT
IDT


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