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PDF ISP1181A Data sheet ( Hoja de datos )
| Número de pieza | ISP1181A | |
| Descripción | Full-speed Universal Serial Bus peripheral controller | |
| Fabricantes | Philips | |
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ISP1181A
Full-speed Universal Serial Bus peripheral controller
Rev. 05 — 08 December 2004
Product data
1. General description
The ISP1181A is a Universal Serial Bus (USB) peripheral controller that complies
with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed
(12 Mbit/s). It provides full-speed USB communication capacity to microcontroller or
microprocessor-based systems. The ISP1181A communicates with the system’s
microcontroller or microprocessor through a high-speed general-purpose parallel
interface.
The ISP1181A supports fully autonomous, multi-configurable Direct Memory Access
(DMA) operation.
The modular approach to implementing a USB peripheral controller allows the
designer to select the optimum system microcontroller from the wide variety available.
The ability to reuse existing architecture and firmware investments shortens
development time, eliminates risks and reduces costs. The result is fast and efficient
development of the most cost-effective USB peripheral solution.
The ISP1181A is ideally suited for application in many personal computer peripherals
such as printers, communication devices, scanners, external mass storage (Zip®
drive) devices and digital still cameras. It offers an immediate cost reduction for
applications that currently use SCSI implementations.
2. Features
s Complies with Universal Serial Bus Specification Rev. 2.0 and most Device Class
specifications
s Supports data transfer at full-speed (12 Mbit/s)
s High performance USB peripheral controller with integrated Serial Interface
Engine (SIE), FIFO memory, transceiver and 3.3 V voltage regulator
s High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface
s Fully autonomous and multi-configuration DMA operation
s Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints
s Integrated physical 2462 bytes of multi-configuration FIFO memory
s Endpoints with double buffering to increase throughput and ease real-time data
transfer
s Seamless interface with most microcontrollers/microprocessors
s Bus-powered capability with low power consumption and low ‘suspend’ current
s 6 MHz crystal oscillator input with integrated PLL for low EMI
s Controllable LazyClock (100 kHz ± 50 %) output during ‘suspend’
s Software controlled connection to the USB bus (SoftConnect™)
s Good USB connection indicator that blinks with traffic (GoodLink™)
1 page  
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
9397 750 13959
Product data
BUS_CONF0 12
TEST3 11
INT 10
TEST2 9
TEST1 8
DACK 7
DREQ 6
EOT 5
SUSPEND 4
WAKEUP 3
GL 2
VBUS 1
ISP1181ABS
25 DATA6
26 DATA5
27 DATA4
28 DATA3
29 DATA2
30 DATA1
31 GND
32 VCC(3.3)
33 AD0
34 A0
35 RD
36 WR
Bottom view
Fig 3. Pin configuration HVQFN48.
004aaa021
6.2 Pin description
Table 2: Pin description
Symbol[1]
Pin
Type Description
TSSOP48 HVQFN48
VCC
REGGND
1
2
44 - supply voltage (3.3 V or 5.0 V)
45 - voltage regulator ground supply
Vreg(3.3)
3
46 - regulated supply voltage (3.3 V ± 10 %)
from internal regulator; used to connect
decoupling capacitor and pull-up resistor on
D+ line;
Remark: Cannot be used to supply external
devices.
D− 4 47 AI/O USB D− connection (analog)
D+ 5 48 AI/O USB D+ connection (analog)
VBUS 6 1 I VBUS sensing input
GL 7 2 O GoodLink LED indicator output (open-drain,
8 mA); the LED is default ON, blinks OFF
upon USB traffic; to connect an LED use a
series resistor of 470 Ω (VCC = 5.0 V) or
330 Ω (VCC = 3.3 V)
WAKEUP
8
3
I wake-up input (edge triggered,
LOW to HIGH); generates a remote
wake-up from ‘suspend’ state
SUSPEND 9 4 O ‘suspend’ state indicator output (4 mA);
used as power switch control output (active
LOW) for powered-off application
Rev. 05 — 08 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 70
5 Page 
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
8. Modes of operation
The ISP1181A has four bus configuration modes, selected via pins BUS_CONF1 and
BUS_CONF0:
Mode 0
Mode 1
Mode 2
Mode 3
16-bit I/O port shared with 16-bit DMA port
reserved
8-bit I/O port shared with 8-bit DMA port
reserved.
The bus configurations for each of these modes are given in Table 3. Typical interface
circuits for each mode are given in Section 21.1.
Table 3:
Mode
0
1
2
3
Bus configuration modes
BUS_CONF[1:0] PIO width
0 0 D[15:1], AD0
0 1 reserved
1 0 D[7:1], AD0
1 1 reserved
DMA width
DMAWD = 0 DMAWD = 1
- D[15:1], AD0
reserved
D[7:1], AD0
reserved
-
reserved
reserved
Description
multiplexed address/data on pin AD0;
bus is shared by 16-bit I/O port and
16-bit DMA port
reserved
multiplexed address/data on pin AD0;
bus is shared by 8-bit I/O port and 8-bit
DMA port
reserved
9. Endpoint descriptions
Each USB peripheral is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the host and the
peripheral. At design time each endpoint is assigned a unique number (endpoint
identifier, see Table 4). The combination of the peripheral address (given by the host
during enumeration), the endpoint number, and the transfer direction allows each
endpoint to be uniquely referenced.
The ISP1181A has 16 endpoints: endpoint 0 (control IN and OUT) plus 14
configurable endpoints, which can be individually defined as
interrupt/bulk/isochronous, IN or OUT. Each enabled endpoint has an associated
FIFO, which can be accessed either via the parallel I/O interface or via DMA.
9.1 Endpoint access
Table 4 lists the endpoint access modes and programmability. All endpoints support
I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is
selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Configuration
Register. A detailed description of the DMA operation is given in Section 10.
9397 750 13959
Product data
Rev. 05 — 08 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 70
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