DataSheet.jp

9FGV0841 の電気的特性と機能

9FGV0841のメーカーはIDTです、この部品の機能は「8-O/P 1.8V PCIe Gen 1-2-3 Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 9FGV0841
部品説明 8-O/P 1.8V PCIe Gen 1-2-3 Clock Generator
メーカ IDT
ロゴ IDT ロゴ 




このページの下部にプレビューと9FGV0841ダウンロード(pdfファイル)リンクがあります。

Total 17 pages

No Preview Available !

9FGV0841 Datasheet, 9FGV0841 PDF,ピン配置, 機能
8-O/P 1.8V PCIe Gen 1-2-3 Clock Generator
w/Zo=100ohms
9FGV0841
DATASHEET
Description
The 9FGV0841 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power PCIe clock family. It has integrated output
terminations providing Zo=100for direction connection to
100transmission lines. The device has 8 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 clock generator
Output Features
8 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo=100
1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
Features/Benefits
Direct connection to 100transmission lines; saves 32
resistors compared to standard PCIe devices
62mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 48-pin 6x6 mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
8
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0841 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.

1 Page





9FGV0841 pdf, ピン配列
9FGV0841 DATASHEET
Pin Descriptions
PIN # PIN NAME
1 vSS_EN_tri
2 GNDXTAL
3 X1_25
4 X2
5 VDDXTAL1.8
6 VDDREF1.8
7 vSADR/REF1.8
8 GNDREF
9 GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG1.8
13 VDDIO
14 vOE0#
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
20 VDD1.8
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
26 DIF3
27 DIF3#
28 vOE3#
29 GNDA
30 VDDA1.8
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
37 vOE5#
38 VDD1.8
39 VDDIO
TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
IN 1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND GND for XTAL
IN Crystal input, Nominally 25.00MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 1.8V
PWR VDD for REF output. nominal 1.8V.
LATCHED Latch to select SMBus Address/1.8V LVCMOS copy of X1/REFIN pin
I/O
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.8V digital power (dirty power)
PWR Power supply for differential outputs
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin for the PLL core.
PWR 1.8V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OCTOBER 18, 2016
3 8-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS


3Pages


9FGV0841 電子部品, 半導体
9FGV0841 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0841. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDxx
Applies to all VDD pins
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5V
3.6V
150
125
UNITS
V
V
V
°C
°C
V
NOTES
1,2
1, 3
1
1
1
1
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Operating Supply Current
IDDAOP
IDDOP
VDDA, All outputs active @100MHz
All VDD, except VDDA and VDDIO, All outputs
active @100MHz
6
12
IDDIOOP
VDDIO, All outputs active @100MHz
28
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
IDDAPD
IDDPD
IDDIOPD
VDDA, DIF outputs off, REF output running
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running
VDDIO, DIF outputs off, REF output running
0.4
5.3
0.04
Powerdown Current
IDDAPD
VDDA, all outputs off
0.4
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
IDDPD All VDD, except VDDA and VDDIO, all outputs off
IDDIOPD
VDDIO, all outputs off
0.6
0.0005
1 Guaranteed by design and characterization, not 100% tested in production.
2 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
9
16
35
1
8
0.1
1
1
0.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
2
2
2
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Duty Cycle
tDC Measured differentially, PLL Mode
Skew, Output to Output
tsk3
Averaging on, VT = 50%
Jitter, Cycle to cycle
tjcyc-cyc
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
45 50 55 % 1,2
43 50 ps 1,2
14 50 ps 1,2
8-O/P 1.8V PCIE GEN 1-2-3 CLOCK GENERATOR W/ZO=100OHMS
6
OCTOBER 18, 2016

6 Page



ページ 合計 : 17 ページ
 
PDF
ダウンロード
[ 9FGV0841 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
9FGV0841

8-O/P 1.8V PCIe Gen 1-2-3 Clock Generator

IDT
IDT


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap