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9FGL08 の電気的特性と機能

9FGL08のメーカーはIDTです、この部品の機能は「8-output 3.3V PCIe Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 9FGL08
部品説明 8-output 3.3V PCIe Clock Generator
メーカ IDT
ロゴ IDT ロゴ 




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9FGL08 Datasheet, 9FGL08 PDF,ピン配置, 機能
8-output 3.3V PCIe Clock Generator
9FGL08
Description
The 9FGL08 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 8 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL08
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL08P1 can be programmed with a
user-defined power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
8 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
9FGL0841 default ZOUT = 100
9FGL0851 default ZOUT = 85
9FGL08P1 factory programmable defaults
1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC-compliant
PCIe Gen2-3 SRIS-compliant
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF 12k-20M phase jitter is <2ps rms when SSC is off
REF phase jitter is <300fs rms, SSC off, and <1.5ps rms,
SSC is On
±100ppm frequency accuracy on all clocks
Block Diagram
DATASHEET
Features/Benefits
Direct connection to 100(xx41) or 85(xx51)
transmission lines; saves 32 resistors compared to
standard PCIe devices
206mW typical power consumption (62mA*3.3V);
eliminates thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
differential output amplitude
33, 85 or 100output impedance for each output
spread spectrum amount
41 and 51 devices contain default configuration; SMBus
interface not required for device operation
P1 device allows factory programming of customer-defined
input/output frequencies and SMBus power up default;
allows exact optimization to customer requirements.
8MHz - 40MHz input frequency with 9FGL08P1 device
(25MHz default); flexibility
OE# pins; support DIF power management
Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
DIF outputs blocked until PLL is locked; clean system
start-up
Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
603-25-150JA4I 25MHz
X2
8
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SSC Capable
PLL
REF
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL08 OCTOBER 19, 2016
1 ©2016 Integrated Device Technology, Inc.

1 Page





9FGL08 pdf, ピン配列
9FGL08 DATASHEET
Pin Descriptions
PIN # PIN NAME
1 vSS_EN_tri
2 GNDXTAL
3 XIN/CLKIN_25
4 X2
5 VDDXTAL3.3
6 VDDREF3.3
7 vSADR/REF3.3
8 GNDREF
9 GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG3.3
13 VDDIO
14 vOE0#
15 DIF0
16 DIF0#
17 vOE1#
18 DIF1
19 DIF1#
20 VDD3.3
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
26 DIF3
27 DIF3#
28 vOE3#
29 GNDA
30 VDDA3.3
31 VDDIO
32 DIF4
33 DIF4#
34 vOE4#
35 DIF5
36 DIF5#
37 vOE5#
38 VDD3.3
39 VDDIO
TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
IN 1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND GND for XTAL
IN Crystal input or Reference Clock input. Nominally 25MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 3.3V
PWR VDD for REF output. nominal 3.3V.
LATCHED Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin
I/O
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V digital power (dirty power)
PWR Power supply for differential outputs
IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 3.3V
PWR Power supply for differential outputs
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin for the PLL core.
PWR 3.3V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply, nominal 3.3V
PWR Power supply for differential outputs
OCTOBER 19, 2016
3 8-OUTPUT 3.3V PCIE CLOCK GENERATOR


3Pages


9FGL08 電子部品, 半導体
9FGL08 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Supply Voltage
IO Supply Voltage
Ambient Operating
Temperature
VDDxxx
VDDIO
TAMB
Supply voltage for core, analog and single-ended
LVCMOS outputs.
Supply voltage for differential Low Power outputs.
Industrial range
3.135 3.3
0.9975 1.05-3.3
-40 25
3.465
3.465
85
V
V
°C
Input High Voltage
Input Low Voltage
VIH
VIL
Single-ended inputs, except SMBus
0.75 VDDx
-0.3
VDDx + 0.3
0.25 VDDx
V
V
Input High Voltage
VIHtri
0.75 VDDx
VDD + 0.3 V
Input Mid Voltage
VIMtri
Single-ended tri-level inputs ('_tri' suffix)
0.4 VDDx 0.5 VDDx 0.6 VDDx
V
Input Low Voltage
VILtri
-0.3
0.25 VDDx
V
Input Current
IIN
Single-ended inputs, VIN = GND, VIN = VDD
-5
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-50
VIN = VDD; Inputs with internal pull-down resistors
5 uA
50 uA
Input Frequency
Fin
XTAL, or X1 input
8 25 40 MHz
Pin Inductance
Lpin
7 nH
Capacitance
CIN
COUT
Logic Inputs, except DIF_IN
Output pin capacitance
1.5
5 pF
6 pF
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.3 1.8 ms
SS Modulation Frequency
OE# Latency
fMOD
tLATOE#
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
30 31.6
12
33 kHz
3 clocks
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
300 us
Tfall tF Fall time of single-ended control inputs
5 ns
Trise
tR Rise time of single-ended control inputs
1 Guaranteed by design and characterization, not 100% tested in production.
5 ns
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 The 9FGLxxP1 devices can be programmed for various input frequencies from 8 to 40MHz. The 9FGLxx41/51 devices use 25MHz.
4
1
1
1
1,2
1
1,3
1,3
1,2
1,2
8-OUTPUT 3.3V PCIE CLOCK GENERATOR
6
OCTOBER 19, 2016

6 Page



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共有リンク

Link :


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