PDF ICS9FG107 Data sheet ( Hoja de datos )

Número de pieza	ICS9FG107
Descripción	Programmable FTG
Fabricantes	IDT
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No Preview Available ! DATASHEET Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks ICS9FG107 Description ICS9FG107 is a Frequency Timing Generator that provides 7 differential output pairs that are compliant to the Intel CK409/CK410 specification. It provides support for PCI-Express, next generation I/ O, and SATA. The part synthesizes several output frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps. ICS9FG107 also provides a copy of the reference clock and 333 MHz PCI output clocks. Frequency selection can be accomplished via strap pins or SMBus control. Features/Benefits • Generates common CPU/PCI Express frequencies from 14.318 MHz or 25 MHz • Crystal or reference input • 7 - 0.7V current-mode differential output pairs • 3 - 33MHz PCI outputs • 1 - REFOUT • Supports Serial-ATA at 100 MHz • Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread • Unused inputs may be disabled in either driven or Hi-Z state for power management. Key Specifications • Output cycle-to-cycle jitter for DIF outputs < 50 ps (<85ps @ 266 MHz) • Output to output skew for DIF outputs < 85 ps • +/-300 ppm frequency accuracy on output clocks • 48-pin SSOP/TSSOP package • Available in RoHS compliant packaging Funtional Block Diagram XIN/CLKIN X2 REFOUT SCLK SDATA DIF_STOP# SEL14M_25M# SPREAD DWNSPRD# OE (6:0) FS (2:0) Control Logic Programmable Spread PLL1 Programmable Frequency Dividers PCICLK (1:0) PCICLK_F DIF (6:0) DIF# (6:0) I REF IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks 1 ICS9FG107 REV F 08/21/07 1 page ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks General SMBus serial interface information for the ICS9FG107 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address DC (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address DD (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controlle r (Host) T starT bit ICS (Sla ve /Re ce ive r) S lave Address DC(H) W R W Rite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - 1 P stoP bit ACK Index Block Read Operation Controlle r (Host) ICS (Sla ve /Re ce ive r) T starT bit Slave Address DC(H) W R W Rite ACK Beginning Byte = N ACK RT Repeat starT Slave Address DD(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks 5 ICS9FG107 REV F 08/21/07 5 Page ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Current Source Output Impedance Zo1 VO = Vx 3000 Ω Voltage High Voltage Low VHigh VLow Statistical measurement on single ended signal using oscilloscope math function. 660 -150 850 150 mV Max Voltage Min Voltage Vovs Vuds Measurement on single ended signal using absolute value. -300 1150 mV Crossing Voltage (abs) Vcross(abs) 250 550 mV Crossing Voltage (var) d-Vcross Variation of crossing over all edges 140 mV Long Accuracy ppm see Tperiod min-max values -300 300 ppm 400MHz nominal 2.4993 2.5008 ns 400MHz spread 2.4993 2.5133 ns 333.33MHz nominal 2.9991 3.0009 ns 333.33MHz spread 2.9991 3.016 ns 266.66MHz nominal 3.7489 3.7511 ns 266.66MHz spread 3.7489 3.77 ns Average period Tperiod 200MHz nominal 200MHz spread 4.9985 4.9985 5.0015 5.0266 ns ns 166.66MHz nominal 5.9982 6.0018 ns 166.66MHz spread 5.9982 6.0320 ns 133.33MHz nominal 7.4978 7.5023 ns 133.33MHz spread 7.4978 5.4000 ns 100.00MHz nominal 9.9970 10.0030 ns 100.00MHz spread 9.9970 10.0533 ns 400MHz nominal/spread 2.4143 ns 333.33MHz nominal/spread 2.9141 ns 266.66MHz nominal/spread 3.6639 ns Absolute min period Tabsmin 200MHz nominal/spread 4.8735 ns 166.66MHz nominal/spread 5.8732 ns 133.33MHz nominal/spread 7.3728 ns 100.00MHz nominal/spread 9.8720 ns Rise Time tr VOL = 0.175V, VOH = 0.525V 175 700 ps Fall Time tf VOH = 0.525V VOL = 0.175V 175 700 ps Rise Time Variation d-tr 125 ps Fall Time Variation d-tf 125 ps Duty Cycle dt3 Measurement from differential wavefrom 45 55 % Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom f not equal 266 MHz Measurement from differential wavefrom f = 266 MHz 50 ps 85 ps 1Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz 3 Figures are for down spread. NOTES 1 1 1 1 1 1 1 1,2 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks 11 ICS9FG107 REV F 08/21/07 11 Page

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