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PDF ICS9FG108 Data sheet ( Hoja de datos )
| Número de pieza | ICS9FG108 | |
| Descripción | Frequency Generator | |
| Fabricantes | IDT | |
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Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DATASHEET
ICS9FG108
Description
ICS9FG108 is a Frequency Timing Generator that provides 8
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express, next
generation I/O, and SATA. The part synthesizes several output
frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal.
The device can also be driven by a reference input clock instead of
a crystal. It provides outputs with cycle-to-cycle jitter of less than 50
ps and output-to-output skew of less than 65 ps. ICS9FG108 also
provides a copy of the reference clock. Frequency selection can be
accomplished via strap pins or SMBus control.
Key Specifications
• Output cycle-to-cycle jitter < 50 ps
• Output to output skew < 65 ps
• +/-300 ppm frequency accuracy on output clocks
• +/-150 ppm frequency accuracy @100 MHz outputs
• 48-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Features/Benefits
• Generates common frequencies from 14.318 MHz or
25 MHz
• Crystal or reference input
• 8 - 0.7V current-mode differential output pairs
• Supports Serial-ATA at 100 MHz
• Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
• Unused inputs may be disabled in either driven or Hi-Z
state for power management.
• Programmable OE Polarity
• M/N Programming
Funtional Block Diagram
XIN/CLKIN
X2
OE(7:0)
OSC
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
8
R EFOU T
DIF(7:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1
ICS9FG108 REV G 04/06/07
1 page  
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
General SMBus serial interface information for the ICS9FG108
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC
(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address DC(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
P stoP bit
ACK
Index Block Read Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address DC(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address DD(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
5
N Not acknowledge
P stoP bit
Byte N + X - 1
ICS9FG108 REV G 04/06/07
5 Page 
ICS9FG108
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP#
DIF
DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_Stop#
DIF
DIF#
DIF Internal
Tdrive_DIF_Stop, 15nS >200mV
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
11
ICS9FG108 REV G 04/06/07
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS9FG108.PDF ] | |
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