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8V74S4622 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 8V74S4622
部品説明 Clock Fanout Buffer/Frequency Divider
メーカ IDT
ロゴ IDT ロゴ 



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8V74S4622 Datasheet, 8V74S4622 PDF,ピン配置, 機能
Clock Fanout Buffer/Frequency Divider
8V74S4622
DATA SHEET
General Description
The 8V74S4622 is a versatile Clock Fanout Buffer/Frequency
Divider. The device supports the selection, division and distribution
of high-frequency clock signals with very low additive phase noise.
The 8V74S4622 uses SiGe technology for an optimum of high clock
frequency and low phase noise performance, combined with high
power supply noise rejection and internal isolation.
Two selectable inputs are supported for differential and single ended
clocks. Each of the two outputs can select a copy or a frequency-
divided input signal. The available frequency divisions are
divide-by-2, 4, 5 and 8. Both outputs support LVDS interfaces. For
each of the two outputs, a synchronous output enabled control is
implemented for stopping the output clock synchronously to the input
clock signal. All device configurations are through a logic pin
interface. The device is packaged in a lead-free (RoHS 6) 20-lead
VFQFN package. The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
• Clock signal selection, frequency-division and distribution
• Two outputs individually select:
• The input signal ÷2, ÷4, ÷5 and ÷8 or
• The input signal without frequency division (input signal is
passed through)
• Two inputs to support single-ended and differential operation
• Differential input supports LVDS and LVPECL signals
• Single-ended input supports LVCMOS signals
• Two differential LVDS outputs
• Maximum Input Frequency (differential input clock): 2000MHz
• Maximum Output Frequency: 2000MHz
• Output skew: 22ps (maximum)
• Additive phase noise RMS, 125MHz, SELn = 0, 12kHz - 20MHz
integration range: 180fs (maximum)
• LVDS output rise/fall time: 260ps (maximum)
• 3.3V core and output supply voltages
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) 4x4 mm2 20-lead VFQFN packaging
Pin Assignment
Block Diagram
20 19 18 17 16
SEL1 1
15 nOE0
IN 2
14 GND
VT 3
8V74S4622
13 nQ1
nIN 4
12 Q1
REFSEL 5
11 VDDO1
6 7 8 9 10
CLK
IN
nIN
VT
REFSEL
N[1:0]
SEL[1:0]
nOE0
nOE1
2x 50
0 fCLK
1
÷N
2
2
0
1 EN
0
1 EN
Q0
nQ0
Q1
nQ1
20-pin, 4mm x 4mm VFQFN Package
8V74S4622 REVISION 1 05/11/15
1
©2015 Integrated Device Technology, Inc.

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Clock Fanout Buffer/Frequency Divider

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