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8V79S674 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 8V79S674
部品説明 LVPECL Clock Divider and Fanout Buffer
メーカ IDT
ロゴ IDT ロゴ 



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8V79S674 Datasheet, 8V79S674 PDF,ピン配置, 機能
Differential-to-3.3V, 2.5V LVPECL
Clock Divider and Fanout Buffer
8V79S674
DATA SHEET
General Description
The 8V79S674 is a clock divider and fanout buffer. The device has
been designed for clock signal division in wireless base station radio
equipment boards. The device is optimized to deliver excellent
additive phase jitter performance. The 8V79S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew LVPECL outputs are available and support clock output
frequencies up to 2500MHz (÷1 frequency division). Outputs can be
disabled to save power consumption if not used. The device is
packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
Clock signal division and distribution
SiGe technology for high-frequency and fast signal rise/fall times
Four low-skew LVPECL clock outputs
Supports frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum frequency: 2500MHz
Maximum output skew: 50ps (maximum)
Maximum LVPECL output rise/fall time: 200ps (maximum)
3.3V or 2.5V core and output supply mode
Supports 1.8V I/O logic levels for all control pins
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN ÷N
nIN
2x 50
VT
VREFAC
Reference Voltage
N[1:0]
nOEA
nOEB
Pulldown
Pulldown
Pulldown
.
8V79S674 REVISION 2 04/10/15
Pin Assignment
Q0
nQ0
Q1
nQ1
15 14 13 12 11
VCC 16
10 Q3
Q0 17
9 nQ3
Q2
nQ2
Q3
nQ3
nQ0 18
nOEA 19
VEE 20
1
8V79S674
8 nOEB
7 N1
6 VEE
2 3 45
20-pin, 4mm x 4mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.

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LVPECL Clock Divider and Fanout Buffer

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