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PDF 8T73S208A-01 Data sheet ( 特性 )

部品番号 8T73S208A-01
部品説明 LVPECL Clock Divider and Buffer
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8T73S208A-01 Datasheet, 8T73S208A-01 PDF,ピン配置, 機能
2.5V, 3.3V Differential LVPECL Clock
Divider and Buffer
REFER TO PCN# N1605-01, Effective Date August 18, 2016
FOR NEW DESIGNS USE PART NUMBER: 8T73S208B-01NLGI
8T73S208A-01
DATA SHEET
General Description
The 8T73S208A-01 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208A-01 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208A-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
Features
One differential input reference clock
Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVPECL outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enable/disabled by I2C interface
Power-up state: all outputs disabled
Output skew: 60ps (maximum)
Output rise/fall times: 350ps (maximum)
Low additive phase jitter, RMS: 182fs (typical)
Full 2.5V and 3.3V supply voltages
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
8T73S208A-01 REVISION 2 05/20/16
1 ©2016 Integrated Device Technology, Inc.

1 Page





8T73S208A-01 pdf, ピン配列
8T73S208A-01 DATA SHEET
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions
Number
1,
32
Name
ADR1, ADR0
Type
Input
Pulldown
Description
I2C Address inputs. LVCMOS/LVTTL interface levels.
2, 7, 18, 23
3, 4
5, 6
8, 17
9, 10
VEE
Q0, nQ0
Q1, nQ1
VCCO
Q2, nQ2
Power
Output
Output
Power
Output
Negative supply pins.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
Output supply pins.
Differential output pair 2. LVPECL interface levels.
11, 12
13, 14
15, 16
19, 20
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Output
Output
Output
Output
Differential output pair 3. LVPECL interface levels.
Differential output pair 4. LVPECL interface levels.
Differential output pair 5. LVPECL interface levels.
Differential output pair 6. LVPECL interface levels.
21, 22
Q7, nQ7
Output
Differential output pair 7. LVPECL interface levels.
24,
25
FSEL0,
FSEL1
Input
Pulldown Frequency divider select controls. See Table 3A for function.
LVCMOS/LVTTL interface levels.
26 IN Input
Non-inverting differential clock input. RT = 50termination to VT.
27
VT
Termination
Input
Input for termination. Both IN and nIN inputs are internally terminated 50
to this pin. See input termination information in Section, “Applications
Information”.
28 nIN Input
Inverting differential clock input. RT = 50termination to VT.
29 VCC Power
Power supply pin.
30
SDA
I/O
Pullup
I2C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output:
open drain.
31
SCL
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
NOTE: Pulldown and Pullup refers to an internal input resistors. See Section, “Table 2. Pin Characteristics” values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
REVISION 2 05/20/16
3 2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER


3Pages


8T73S208A-01 電子部品, 半導体
8T73S208A-01 DATA SHEET
Table 4B. LVCMOS/LVTTL Input DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FSEL[1:0], ADR[1:0]
VCC = 3.3V ± 5%
2.2
VCC + 0.3V
V
VIH
Input
SCL, SDA
High Voltage1
VCC = 3.3V ± 5%
FSEL[1:0], ADR[1:0]
VCC = 2.5V ± 5%
SCL, SDA
VCC = 2.5V ± 5%
FSEL[1:0], ADR[1:0]
VCC = 3.3V ± 5%
VIL
Input
SCL, SDA
Low Voltage1 FSEL[1:0], ADR[1:0]
VCC = 3.3V ± 5%
VCC = 2.5V ± 5%
SCL, SDA
VCC = 2.5V ± 5%
IIH
Input
High Current
FSEL[1:0], ADR[1:0]
SCL, SDA
VCC = VIN = 2.625 or 3.465V
VCC = VIN = 2.625 or 3.465V
IIL
Input
Low Current
FSEL[1:0], ADR[1:0]
SCL, SDA
VCC = 2.625 or 3.465V, VIN = 0V
VCC = 2.625 or 3.465V, VIN = 0V
NOTE 1: VIL should not be lower than -0.3V and VIH should not be higher than VCC + 0.3V.
2.4
1.7
1.9
-0.3
-0.3
-0.3
-0.3
-10
-150
VCC + 0.3V
VCC + 0.3V
VCC + 0.3V
0.8
0.8
0.7
0.5
150
10
V
V
V
V
V
V
V
µA
µA
µA
µA
Table 4C. Differential Input DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIN
VCMR
Input Voltage Swing1 IN, nIN
Common Mode Input Voltage1, 2
0.15
1.2
1.2
VCC – (VPP/2)
V
V
VDIFF_IN Differential Input Voltage Swing
0.3 2.4 V
RIN
Input Resistance
IN, nIN
IN, nIN to VT
40 50
60
RIN_DIFF
Differential
Input Resistance
IN, nIN
IN to nIN, VT = Open
80 100 120
NOTE 1: VIL should not be less than -0.3V and VIH should not be greater than VCC
NOTE 2: Common Mode Input Voltage is defined as the cross point.
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER
6
REVISION 2 05/20/16

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LVPECL Clock Divider and Buffer

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