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8SLVD1204-33 の電気的特性と機能

8SLVD1204-33のメーカーはIDTです、この部品の機能は「LVDS Output Fanout Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 8SLVD1204-33
部品説明 LVDS Output Fanout Buffer
メーカ IDT
ロゴ IDT ロゴ 




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8SLVD1204-33 Datasheet, 8SLVD1204-33 PDF,ピン配置, 機能
2:4, LVDS Output Fanout Buffer
8SLVD1204-33
DATA SHEET
General Description
The 8SLVD1204-33 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1204-33
is characterized to operate from a 3.3V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1204-33 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
Four low skew, low additive jitter LVDS output pairs
Two selectable differential clock input pairs
Differential PCLKx, nPCLKx pairs can accept the following
differential input levels: LVDS, LVPECL
Maximum input clock frequency: 2GHz
LVCMOS/LVTTL interface levels for the control input select pin
Output skew: 20ps (maximum)
Propagation delay: 310ps (maximum)
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
10kHz - 20MHz: 100fs (maximum)
Full 3.3V supply voltage
Lead-free (RoHS 6), 16-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
VDD
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
GND GND
VDD
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
GND GND
VDD
SEL Pullup/Pulldown
VREF
GND
Reference
Voltage
Generator
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
12 11 10
Q2 13
9
8 VREF
nQ2 14
Q3 15
8SLVD1204-33
8XXXXXX
7 nPCLK0
6 PCLK0
nQ3 16
5 VDD
12 3 4
16-pin, 3mm x 3mm VFQFN Package
8SLVD1204-33 REVSION B 03/11/15
1 ©2015 Integrated Device Technology, Inc.

1 Page





8SLVD1204-33 pdf, ピン配列
8SLVD1204-33 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VDD
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
VREF Current (Sink/Source), IREF
Maximum Junction Temperature, TJ,MAX
Storage Temperature, TSTG
ESD - Human Body Model, NOTE 1
ESD - Charged Device Model, NOTE 1
Rating
4.6V
-0.5V to VDD + 0.5V
10mA
15mA
±2mA
125°C
-65C to 150C
2000V
1500V
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
Electrical Characteristics
Table 4A. Power Supply Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VDD Power Supply Voltage
SEL = 0 or 1; fREF = 100MHz; Q0 to Q3
terminated 100between nQx, Qx
3.135
IDD Power Supply Current
SEL = 0 or 1; fREF = 800MHz; Q0 to Q3
terminated 100between nQx, Qx
SEL = 0 or 1; fREF = 2GHz; Q0 to Q3
terminated 100between nQx, Qx
Typical
3.3
86
86
86
Maximum
3.465
100
Units
V
mA
100 mA
100 mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIH Input High Voltage SEL
VIL Input Low Voltage SEL
IIH Input High Current SEL
IIL Input Low Current SEL
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
0.7 * VDD
-0.3
-150
Typical
Maximum
VDD + 0.3
0.2 * VDD
150
Units
V
V
µA
µA
REVSION B 03/11/15
3 2:4, LVDS OUTPUT FANOUT BUFFER


3Pages


8SLVD1204-33 電子部品, 半導体
8SLVD1204-33 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz, VPP = 1V,
Integration Range (12kHz to 20MHz) = 67fs (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
2:4, LVDS OUTPUT FANOUT BUFFER
6
REVSION B 03/11/15

6 Page



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8SLVD1204-33

LVDS Output Fanout Buffer

IDT
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