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ICS8S89833I の電気的特性と機能

ICS8S89833IのメーカーはIDTです、この部品の機能は「1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination」です。


製品の詳細 ( Datasheet PDF )

部品番号 ICS8S89833I
部品説明 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination
メーカ IDT
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ICS8S89833I Datasheet, ICS8S89833I PDF,ピン配置, 機能
Low Skew, 1-To-4 Differential-To-LVDS
Fanout Buffer w/Internal Termination
ICS8S89833I
DATA SHEET
General Description
The ICS8S89833I is a high speed 1-to-4 Differential-to-LVDS Fanout
Buffer with Internal Termination. The ICS8S89833I is optimized for
high speed and very low output skew, making it suitable for use in
demanding applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated differential
input and VREF_AC pin allow other differential signal families such as
LVPECL, LVDS, and CML to be easily interfaced to the input with
minimal use of external components. The device also has an output
enable pin which may be useful for system test and debug purposes.
The ICS8S89833I is packaged in a small 3mm x 3mm 16-pin
VFQFN package which makes it ideal for use in space-constrained
applications.
Features
Four differential LVDS outputs
IN, nIN input pair can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: 2GHz
Cycle-to-cycle jitter, RMS: 3.5ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Output skew: 30ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation Delay: 600ps (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN
50
VT
50
nIN
VREF_AC
EN Pullup
DQ
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q0 1
12 IN
nQ0 2
11 VT
Q1 3
10 VREF_AC
nQ1 4
9 nIN
5 6 78
ICS8S89833I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89833AKI REVISION A JULY 13, 2010
1
©2010 Integrated Device Technology, Inc.

1 Page





ICS8S89833I pdf, ピン配列
ICS8S89833I Data Sheet
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION
Function Tables
Table 3. Control Input Function Table
Inputs
Outputs
IN nIN EN
Q[0:3]
nQ[0:3]
011
0
1
101
1
0
X X 0 Disabled LOWNOTE 1 Disabled HIGHNOTE 1
NOTE 1: On the next negative transition of the input signal (IN).
EN
nIN
VIN
IN
VDD/2
tS
nQx tPD
Qx
Figure 1. EN Timing Diagram
VDD/2
tH
VOD
ICS8S89833AKI REVISION A JULY 13, 2010
3
©2010 Integrated Device Technology, Inc.


3Pages


ICS8S89833I 電子部品, 半導体
ICS8S89833I Data Sheet
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tPD
Output Frequency
Propagation Delay,
(Differential); NOTE 1
IN-to-Qx
tsk(o) Output Skew; NOTE 2, 3
tsk(pp) Part-to-Part Skew; NOTE 3, 4
tjit(cc) Cycle-to-Cycle Jitter, RMS; NOTE 5, 6
ƒ= 622.08MHz,
tjit
Buffer Additive Jitter; RMS; refer to
Additive Phase Jitter Section
Integration Range: 12kHz - 20MHz
ƒ 156.25MHz,
Integration Range: 12kHz - 20MHz
tS
Clock Enable
Setup Time
EN to IN/nIN
tH
Clock Enable
Hold Time
EN to IN/nIN
tR / tF Output Rise/Fall Time
20% – 80%
Minimum Typical
400
0.03
Maximum
2
600
30
200
3.5
0.25
300
500
75 200
Units
GHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters characterized at 1.4GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: Tested at ƒ 750MHz.
NOTE 6: The cycle-to-cycle jitter is dependent on the input source and measurement equipment.
ICS8S89833AKI REVISION A JULY 13, 2010
6
©2010 Integrated Device Technology, Inc.

6 Page



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部品番号部品説明メーカ
ICS8S89833I

1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination

IDT
IDT


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