PDF 6V49205B Data sheet ( Hoja de datos )

Número de pieza	6V49205B
Descripción	Freescale P10XX and P20XX System Clock w/Selectable DDR Frequency
Fabricantes	IDT
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No Preview Available ! Freescale P10XX and P20XX System Clock w/Selectable DDR Frequency 6V49205B DATASHEET General Description The 6V49205B is a main clock for Freescale P10xx and P20xx-based systems. It has a selectable System CCB clock and 2 DDRCLK speeds – 100M or 66.66M. The 6V49205B also provides LP-HCSL PCIe outputs for low power and reduced board space. Output Features • 1 - Sys_CCB 3.3V LVCMOS output @ 100M/83.33M/ 80M/66.66M • 1 - DDRCLK 3.3V LVCMOS output @ 100M or 66.66M 1 • 1 - 125M 3.3V LVCMOS output • 6 - LP-HCSL PCIe pairs selectable @ 100M or 125M • 6 - 25MHz 3.3V LVCMOS outputs • 2 - 2.048M 3.3V LVCMOS outputs • 2 - USB 3.3V LVCMOS outputs @12M or 24M Key Specifications • PCIe Gen1-2-3 compliant • <3p rms phase noise on REF outputs Recommended Application System Clock for Freescale P10xx and P20xx-based designs Features • Replaces 11 crystals, 2 oscillators and 3 clock generators; lowers cost, power and area • Integrated terminations on LP-HCSL PCIe outputs; eliminate 24 resistors, saving 41mm2 of board area • Industrial temperature range operation; supports demanding environmental conditions • Advanced 3.3V CMOS process; high-performance, low-power • Supports independent spread spectrum on Sys_CCB/DDRCLK and PCIe outputs • Available in space-saving 7x7mm 48-pin VFQFPN with 0.5mm pad pitch; reduced board space without the need for fine-pitch assembly techniques Block Diagram SCLK SDATA ^FS0 ^FS1 ^SEL100#_66 ^SELPCIE125#_100 X1 25MHz Crystal X2 Control Logic Crystal Oscillator PLL1 (SS) PLL4 (SS) PLL3 (non- SS) PLL2 (non- SS) 100MHz GND Sys_CCB DDRCLK PCIe_L(5:0) USB_CLK(2:1) 2.048M(1:0) 125M REF(5:0) Note 1: For DDR Clock: Processor core and I/O supply rails must be ramped with VDD3P3 or earlier. Clock signal will be clamped LOW and output clock will be 100MHz if this is not followed (see diagram below). VDD3P3 DDRCLK R40 10K R39 10K 6V49205B REVISION R 11/23/16 1 ©2016 Integrated Device Technology, Inc. 1 page 6V49205B DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 6V49205B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER Maximum Supply Voltage SYMBOL VDDxxx CONDITIONS Supply Voltage Maximum Input Voltage VIH Referenced to GND Minimum Input Voltage VIL Referenced to GND Storage Temperature Ts - JunctionTemperature Input ESD protection Tj ESD prot - Human Body Model NOTES on Absolute Max Parameters 1 Operation under these conditions is neither implied, nor guaranteed. MIN TYP MAX UNITS 4.6 V VDD + 0.5 V GND - 0.5 V -65 2000 150 °C 125 °C V Notes 1 1 1 1 1 Electrical Characteristics - Input/Supply/Common Output DC Parameters TAMB = -40 to +85°C; VDD = 3.3 V +/-5%, All outputs driving test loads (unless noted otherwise). PARAMETER SYMBOL CONDITIONS Ambient Operating Temp Supply Voltage TAMB VDDxxx - Supply Voltage Power supply Ramp Time TPWRRMP Power supply ramp must be montonic Latched Input High Voltage VIH_LI Single-ended Latched Inputs Latched Input Low Voltage VIL_LI Single-ended Latched Inputs Input Leakage Current IIN VIN = VDD , VIN = GND Operating Supply Current IDDOP3.3 All outputs loaded and running Input Frequency Fi MIN -40 3.135 2.1 VSS - 0.3 -5 23 TYP MAX 25 85 3.3 3.465 4 VDD + 0.3 0.8 5 119 155 25 27 UNITS °C V ms V V uA mA MHz Pin Inductance Lpin 57 nH Input Capacitance CIN COUT Logic Inputs Output pin capacitance 1.5 3 5 5 6 pF pF Clk Stabilization CINX TSTAB X1 & X2 pins From VDD Power-Up or de-assertion of PD to 1st clock 56 3.2 5 pF ms Tfall_SE Trise_SE TFALL TRISE Fall/rise time of all 3.3V control inputs from 20-80% 10 ns 10 ns SMBus Voltage VDD 2.7 3.3 V Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time VOLSMB IPULLUP TRI2C @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) 4 0.4 1000 V mA ns SCLK/SDATA Clock/Data Fall Time TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns SMBus Operating Frequency FSMBUS 400 kHz NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Signal is required to be monotonic in this region. 2 Input leakage current does not include inputs with pull-up or pull-down resistors 3 For margining purposes only. Normal operation should have Fin =25MHz Notes 2 3 1 1 REVISION R 11/23/16 5 FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY 5 Page 6V49205B DATASHEET Byte 6 PCI Express Amplitude Control Register Bit Name 7 PCIE_AMP1 6 PCIE_AMP0 5 SEL100#_66 Description PCI Express Amplitude Control DDRCLK latch select 4 SELPCIE125#_100 PCI Express latch select 3 Reserved 2 Reserved Reserved Reserved 1 Reserved Reserved 0 Reserved Reserved Byte 7 Revision and Vendor ID Register Bit Name Description 7 REV ID 6 REV ID 5 REV ID 4 REV ID Revision ID 3 Vendor ID 2 Vendor ID 1 Vendor ID Vendor ID 0 Vendor ID Byte 8 Byte Count Register Bit Name Description 7 BC7 6 BC6 5 BC5 4 BC4 3 BC3 Byte Count Programming b(7:0) 2 BC2 1 BC1 0 BC0 Type RW RW R R RW RW RW RW 01 See Table 4: PCIe Amplitude Selection Table 100MHz 66MHz 125MHz 100MHz -- -- -- -- Default 0 1 latch latch 0 1 0 1 Type R R R R R R R R 0 - - - - - - - - 1 Default -0 -0 -0 -1 -0 -0 -0 -1 Type RW RW RW RW RW RW RW RW 01 Writing to this register will configure how many bytes will be read back. Default 0 0 0 0 0 1 0 1 Recommended Crystal Characteristics PARAMETER Frequency Resonance Mode Frequency Tolerance @ 25°C Frequency Stability, ref @ 25°C Over Operating Temperature Range Temperature Range (commerical) Temperature Range (industrial) Equivalent Series Resistance (ESR) Shunt Capacitance (CO) Load Capacitance (CL) Drive Level Aging per year VALUE 25 Fundamental ±20 ±20 0~70 -40~85 50 7 8 0.1 ±5 UNITS MHz - PPM Max PPM Max °C °C Ω Max pF Max pF Max mW Max PPM Max NOTES 1 1 1 1 1 1 1 1 1 1 1 REVISION R 11/23/16 11 FREESCALE P10XX AND P20XX SYSTEM CLOCK W/SELECTABLE DDR FREQUENCY 11 Page

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