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PL123-05 の電気的特性と機能

PL123-05のメーカーはMicrel Semiconductorです、この部品の機能は「Low Skew Zero Delay Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 PL123-05
部品説明 Low Skew Zero Delay Buffer
メーカ Micrel Semiconductor
ロゴ Micrel Semiconductor ロゴ 




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PL123-05 Datasheet, PL123-05 PDF,ピン配置, 機能
PL123-05/-09
FEATURES
Low Skew Zero Delay Buffer
DESCRIPTION
Frequency Range 10MHz to 134 MHz
Output Options:
o 5 outputs PL123-05
o 9 outputs PL123-09
Zero input - output delay
Optional Drive Strength:
Standard (8mA) PL123-05/-09
High (12mA) PL123-05H/-09H
3.3V, ±10% operation
Available in Commercial and Industrial temperature
ranges
Available in 16-Pin SOP or TSSOP (PL123-09),
and 8-Pin SOP (PL123-05) packages
The PL123-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123-05) or two (PL123-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123-09 allows control of the banks of
outputs by using the S1 and S2 inputs as shown in the
Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF PLL
Mux
S1 Selector
Inputs
S2 (PL123-09 Only)
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF
CLKA2
CLKA1
GND
1
2
3
4
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
8 CLKOUT
7 CLKA4
6 VDD
5 CLKA3
16 CLKOUT
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13 Page 1

1 Page





PL123-05 pdf, ピン配列
PL123-05/-09
Low Skew Zero Delay Buffer
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 
50line
To CMOS Input
Connect a 33 series
resistor at each of the output
clocks to enhance the
stability of the output signal
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13 Page 3


3Pages


PL123-05 電子部品, 半導体
SWITCHING WAVEFORMS
Duty Cycle Timing
1.4V
PL123-05/-09
Low Skew Zero Delay Buffer
t1
t2
1.4V
All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
t3
Output-Output Skew
OUTPUT
1.4V
2.0V
0.8V
t4
3.3V
V
0V
OUTPUT
Input-Output Propagation Delay
INPUT VDD/2
1.4V
t5
OUTPUT
Device-Device Skew
CLKOUT, Device 1
VDD/2
t6
VDD/2
CLKOUT, Device 2
VDD/2
t7
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13 Page 6

6 Page



ページ 合計 : 9 ページ
 
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[ PL123-05 データシート.PDF ]


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共有リンク

Link :


部品番号部品説明メーカ
PL123-05

Low Skew Zero Delay Buffer

Micrel Semiconductor
Micrel Semiconductor
PL123-09

Low Skew Zero Delay Buffer

Micrel Semiconductor
Micrel Semiconductor


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