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ADP5071 の電気的特性と機能

ADP5071のメーカーはAnalog Devicesです、この部品の機能は「DC-to-DC Switching Regulator」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADP5071
部品説明 DC-to-DC Switching Regulator
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADP5071 Datasheet, ADP5071 PDF,ピン配置, 機能
Data Sheet
2 A/1.2 A DC-to-DC Switching Regulator with
Independent Positive and Negative Outputs
ADP5071
FEATURES
Wide input supply voltage range: 2.85 V to 15 V
Generates well regulated, independently resistor
programmable VPOS and VNEG outputs
Boost regulator to generate VPOS output
Adjustable positive output to 39 V
Integrated 2.0 A main switch
Optional single-ended primary-inductor converter
(SEPIC) configuration for automatic step-up/step-down
Inverting regulator to generate VNEG output
Adjustable negative output to VIN − 39 V
Integrated 1.2 A main switch
True shutdown for both positive and negative outputs
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Individual precision enable and flexible start-up sequence
control for symmetric start, VPOS first, or VNEG first
Out-of-phase operation
UVLO, OCP, OVP, and TSD protection
4 mm × 4 mm, 20-lead LFCSP and 20-lead TSSOP
−40°C to +125°C junction temperature range
Supported by the ADIsimPower tool set
APPLICATIONS
Bipolar amplifiers, ADCs, DACs, and multiplexers
Charge-coupled device (CCD) bias supply
Optical module supply
RF power amplifier (PA) bias
GENERAL DESCRIPTION
The ADP5071 is a dual high performance dc-to-dc regulator that
generates independently regulated positive and negative rails.
The input voltage range of 2.85 V to 15 V supports a wide variety of
applications. The integrated main switch in both regulators enables
generation of an adjustable positive output voltage up to +39 V
and a negative output voltage down to −39 V below input voltage.
The ADP5071 operates at a pin selected 1.2 MHz/2.4 MHz
switching frequency. The ADP5071 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. Both regulators implement
programmable slew rate control circuitry for the MOSFET
driver stage to reduce electromagnetic interference (EMI).
Flexible start-up sequencing is provided with the options of
manual enable, simultaneous mode, positive supply first, and
negative supply first.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
TYPICAL APPLICATION CIRCUIT
RC1
CC1
CVREG
ADP5071
SS INBK
COMP1
EN1
SW1
VREG
FB1
VIN
CIN1
RC2
CC2
PVIN1
PVIN2
PVINSYS
EN2
PGND
VREF
COMP2
FB2
SYNC/FREQ
SLEW
SEQ AGND
SW2
L1
D1
RFT1
RFB1
CVREF
RFB2
RFT2
D2
L2
VPOS
COUT1
COUT2
VNEG
Figure 1.
The ADP5071 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up. During
shutdown, both regulators completely disconnect the loads from
the input supply to provide a true shutdown.
Other key safety features in the ADP5071 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The ADP5071 is available in a 20-lead LFCSP or in a 20-lead
TSSOP and is rated for a −40°C to +125°C junction temperature
range.
Table 1. Family Models
Model
Boost Switch (A)
Inverter Switch (A)
ADP5070
ADP5071
1.0
2.0
0.6
1.2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





ADP5071 pdf, ピン配列
ADP5071
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
PWM Mode................................................................................. 14
PSM Mode ................................................................................... 14
Undervoltage Lockout (UVLO) ............................................... 14
Oscillator and Synchronization ................................................ 14
Internal Regulators ..................................................................... 14
Precision Enabling...................................................................... 15
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Added 20-Lead TSSOP ......................................................Universal
Change to Pull-Down Resistance Parameter, Table 2.................. 3
Changes to Table 3 and Table 4....................................................... 5
Added Figure 3, Renumbered Sequentially .................................. 6
Changes to Figure 37 Caption to Figure 39 Caption ................. 13
Changes to Internal Regulators Section ...................................... 14
Change to Soft Start Section.......................................................... 15
Changes to Component Selection Section .................................. 17
Changes to Output Capacitors Section, Soft Start Resistor Section,
and Diodes Section......................................................................... 18
Changes to Figure 52 Caption....................................................... 26
Added Figure 53.............................................................................. 26
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
2/15—Revision 0: Initial Version
Data Sheet
Soft Start ...................................................................................... 15
Slew Rate Control....................................................................... 15
Current-Limit Protection ............................................................ 15
Overvoltage Protection.............................................................. 15
Thermal Shutdown .................................................................... 15
Start-Up Sequence...................................................................... 15
Applications Information .............................................................. 17
ADIsimPower Design Tool ....................................................... 17
Component Selection ................................................................ 17
Loop Compensation .................................................................. 20
Common Applications .............................................................. 22
Super Low Noise With Optional LDOs................................... 24
SEPIC Step-Up/Step-Down Operation ................................... 25
Layout Considerations............................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
Rev. A | Page 2 of 27


3Pages


ADP5071 電子部品, 半導体
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
PVIN1, PVIN2, PVINSYS
INBK
SW1
SW2
PGND, AGND
VREG
EN1, EN2, FB1, FB2, SYNC/FREQ
COMP1, COMP2, SLEW, SS,
SEQ, VREF
Operating Junction
Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +18 V
−0.3 V to PVIN1 + 0.3 V
−0.3 V to +40 V
PVIN2 − 40 V to PVIN2 + 0.3 V
−0.3 V to +0.3 V
−0.3 V to lower of PVINSYS +
0.3 V or +6 V
−0.3 V to +6 V
−0.3 V to VREG + 0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ADP5071
THERMAL RESISTANCE
θJA and ΨJT are based on a 4-layer printed circuit board (PCB)
(two signal and two power planes) with nine thermal vias
connecting the exposed pad to the ground plane as recommended
in the Layout Considerations section. θJC is measured at the top
of the package and is independent of the PCB. The ΨJT value is
more appropriate for calculating junction to case temperature in
the application.
Table 4. Thermal Resistance
Package Type
θJA
20-Lead LFCSP
60.2
20-Lead TSSOP
58.5
θJC ΨJT Unit
36.5 0.63 °C/W
35.0 0.60 °C/W
ESD CAUTION
Rev. A | Page 5 of 27

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