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PDF 1EDI30J12CP Data sheet ( Hoja de datos )
| Número de pieza | 1EDI30J12CP | |
| Descripción | Single JFET Driver IC | |
| Fabricantes | Infineon | |
| Logotipo |  |
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1EDI EiceDRIVER™ Enhanced
1EDI30J12CP
Single JFET Driver IC
Preliminary Datasheet
Rev. 1.3, November 2014
Industrial Power Control
1 page  
EiceDRIVER™ Enhanced
1EDI30J12CP
Pin Configuration and Description
1 Pin Configuration and Description
The pin configuration for 1EDI30J12CP in a PG-DSO-19-4 wide body package is shown in Figure 1 and Table 1.
Figure 1
N.C.
1
20
BSEN
2
19
CLJFG
3
18
VREG
4
17
N.C.
5
VEE2
6
15
MDrv
7
14
JFDrv
8
13
VCC2
9
12
N.C.
10
11
PG-DSO-19-4 (300mil)
Pin Configuration PG-DSO-19-4
N.C.
VCC1
IN
GND1
EN
N.C.
N.C.
N.C.
N.C.
Table 1 Pin Configuration 1EDI30J12CP in PG-DSO-19-4, Wide Body
Pin Symbol Description
1 N.C.
Internally not connected1)
2 BSEN Bootstrap Enable
For bootstrap operation connect this pin to VCC2, for non bootstrap operation to VREG
3 CLJFG Reserved2)
4 VREG Voltage Regulator Output
VREG is the output of the integrated linear regulator and the negative power supply for the gate
drivers
5 N.C.
Internally not connected1)
6 VEE2
Negative Power Supply Output Side
VEE2 is the input of the integrated linear regulator
7 MDrv
MOSFET Driver Output
8 JFDrv JFET Driver Output
9 VCC2 Positive Power Supply Output Side
VCC2 is the positive supply input of the JFET driver and MOSFET driver, connected to the
sources of the JFET and the MOSFET
10 N.C.
Internally not connected1)
11 N.C.
Internally not connected1)
12 N.C.
Internally not connected1)
13 N.C.
Internally not connected1)
14 N.C.
Internally not connected1)
Preliminary Datasheet
4
Rev. 1.3, 2014-11-12
5 Page 
HV supply
VCC1
-25V AUX
Start up auxiliary supply
V VCC1on
EiceDRIVER™ Enhanced
1EDI30J12CP
Functional Description
VVC C 1 o ff
IN
EN
Output signals referenced to VCC2
VEE2
VVJFET _pinch_off
VREG
MDrv
V VREGon
VVR EGo ff
JFDrv
tPD ON
tPD OFF
Figure 5
tPD ON _ EN
tPDOFF _EN
Principle start up with the auxiliary supplies not present when voltage is applied over the
switch (Signal names are chosen equivalent to the pin names of the driver)
3.2.4
Bootstrap supply mode and start up
In bootstrap supply mode, the capacitors at VEE2 and VREG are charged to the pinch off voltage of the JFET as
described in Chapter 3.2.3 (Infineon CoolSiCTM JFET family has the lowest gate threshold voltage at -12 V). When
the BSEN pin is connected to VCC2 the bootstrap supply mode is active. In this case a lower UVLO threshold is
used and the driver is active at approximately -9.0 V.
After passing this lower UVLO threshold the driver is ready to receive IN signals from the input stage. This input
signal is transferred to a switching logic which turns on the p-channel MOSFET. After the VMDrv has passed the
MOSFET gate turn on threshold the JFET is turned on. The voltage drop across the MOSFET and JFET channel
is nearly zero. The potential of VCC2 is identical to JFET drain voltage. A negative supply related to the JFET drain
(positive potential of DC-link capacitor, half bridge supply) can charge the input capacitor CVEE2 through a high
voltage bootstrap diode. An example of a high-side bootstrap supply can be seen in Figure 6.
If the input stage is sending a low to the driving stage, first the JFET is turned off. After the JFDrv has passed the
off threshold the MOSFET is turned off.
The propagation delay in bootstrap mode is therefore enlarged by the MOSFET gate charging time. After VREG
has passed the higher normal UVLO level, the MOSFET is permanently kept on and the delay changes to the fast
Preliminary Datasheet
10
Rev. 1.3, 2014-11-12
11 Page | ||
| Páginas | Total 28 Páginas | |
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