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MC74HC4060 の電気的特性と機能

MC74HC4060のメーカーはMotorola Semiconductorsです、この部品の機能は「14-Stage Binary Ripple Counter」です。


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部品番号 MC74HC4060
部品説明 14-Stage Binary Ripple Counter
メーカ Motorola Semiconductors
ロゴ Motorola Semiconductors ロゴ 




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MC74HC4060 Datasheet, MC74HC4060 PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
14-Stage Binary Ripple
Counter with Oscillator
High–Performance Silicon–Gate CMOS
The MC54/74HC4060 is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 master–slave flip–flops and an oscillator with a
frequency that is controlled either by a crystal or by an RC circuit connected
externally. The output of each flip–flop feeds the next, and the frequency at
each output is half that of the preceding one. The state of the counter
advances on the negative–going edge of Osc In. The active–high Reset is
asynchronous and disables the oscillator to allow very low power consump-
tion during standby operation.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may need to be gated with Osc Out 2 of the HC4060.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
LOGIC DIAGRAM
OSC OUT 1 OSC OUT 2
10 9
OSC IN 11
7 Q4
5 Q5
4 Q6
6 Q7
14 Q8
13 Q9
15 Q10
1 Q12
2 Q13
3 Q14
RESET 12
PIN 16 = VCC
PIN 8 = GND
MC54/74HC4060
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDT
Ceramic
Plastic
TSSOP
PIN ASSIGNMENT
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
GND 8
16 VCC
15 Q10
14 Q8
13 Q9
12 RESET
11 OSC IN
10 OSC OUT 1
9 OSC OUT 2
Clock
X
FUNCTION TABLE
Reset
L
L
H
Output State
No Change
Advance to Next State
All Outputs are Low
10/95
© Motorola, Inc. 1995
1 REV 6

1 Page





MC74HC4060 pdf, ピン配列
MC54/74HC4060
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (Continued)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Parameter
Minimum High–Level Output
Voltage (Osc Out 1, Osc Out 2)
Test Conditions
vVin = VCC or GND
IIoutI 20 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvVin=VCCorGNDIIoutI 1.0mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvIIoutI 1.3mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
vMaximum Low–Level Output
Voltage (Osc Out 1, Osc Out 2)
Vin = VCC or GND
IIoutI 20 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvVin=VCCorGNDIIoutI 1.0mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvIIoutI 1.3mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin Maximum Input Leakage Current Vin = VCC or GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 4.
VCC
V
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfmax
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
tPHL
Maximum Propagation Delay, QN to QN + 1
(Figures 3 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTES:
Maximum Input Capacitance
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
1.9 1.9 1.9
4.4 4.4 4.4
5.9 5.9 5.9
3.98 3.84 3.70
5.48 5.34 5.20
0.1 0.1 0.1
0.1 0.1 0.1
0.1 0.1 0.1
0.26 0.33 0.40
0.26 0.33 0.40
± 0.1
± 1.0
± 1.0
8 80 160
Unit
V
V
µA
µA
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
5.0 4.0 3.4
25 20 17
29 24 20
530 665 795
106 133 159
91 114 135
1600
320
272
2000
400
344
2400
480
408
240 300 360
48 60 72
41 51 61
125 155 190
25 31 38
21 26 32
75 95 110
15 19 22
13 16 19
10 10 10
Unit
MHz
ns
ns
ns
ns
ns
pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
* For TA = 25_C and CL = 50 pF, typical propagation delay from Osc In to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [205 + 107.5(N – 1)] ns
VCC = 4.5 V: tP = [41 + 21.5(N – 1)] ns
VCC = 6.0 V: tP = [35 + 18.3(N – 1)] ns
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
35 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA


3Pages


MC74HC4060 電子部品, 半導体
MC54/74HC4060
RESET 12
11 OSC IN
10 OSC OUT 1
Rf
R1
C1 C2
9 OSC OUT 2
Figure 6. Pierce Crystal Oscillator Circuit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTable 1. Crystal Oscillator Amplifier Specifications
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA = 25_C (Input = Pin 11, Output = Pin 10)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎType
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Resistance, Rin
Output Impedance, Zout (4.5 V supply)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance, Cin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Capacitance, Cout
Series Capacitance, Ca
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3 Vdc supply
Open loop voltage
4 Vdc supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎgain with output at
5 Vdc supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfull swing, α
6 Vdc supply
Positive Reactance (Pierce)
60 Mminimum
200 (see text)
5 pF typical
7 pF typical
5 pF typical
5.0 expected minimum
4.0 expected minimum
3.3 expected minimum
3.1 expected minimum
PIERCE CRYSTAL OSCILLATOR DESIGN
RS LS CS
1 21
2 1 Re Xe 2
CO
Values are supplied by crystal manufacturer (parallel resonant crys-
tal)
Figure 7. Equivalent Crystal Networks
Rs
jXLs
–jXCs
Zload
–jXCo
–jXC2
–jXC
R
Rload
Xload
NOTE: C = C1 + Cin and R = R1 + Rout. Co is considered as part of the
load. Ca and Rf typically have minimal effect below 2 MHz.
Figure 8. Series Equivalent Crystal Load
Ca
Cin
Cout
Values are listed in Table 1.
Figure 9. Parasitic Capacitances
of the Amplifier
MOTOROLA
6 High–Speed CMOS Logic Data
DL129 — Rev 6

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共有リンク

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部品番号部品説明メーカ
MC74HC4060

14-Stage Binary Ripple Counter

Motorola Semiconductors
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MC74HC4060A

14-Stage Binary Ripple Counter

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