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54LS42 データシート PDF ( 特性, スペック, ピン接続図 )

部品番号 54LS42
部品説明 BCD/Decimal Decoders
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 
プレビュー
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54LS42 Datasheet, 54LS42 PDF,ピン配置, 機能
June 1989
54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders
General Description
These BCD-to-decimal decoders consist of eight inverters
and ten four-input NAND gates The inverters are connect-
ed in pairs to make BCD input data available for decoding
by the NAND gates Full decoding of input logic ensures
that all outputs remain off for all invalid (10–15) input condi-
tions
Connection Diagram
Dual-In-Line Package
TL F 6365 – 1
Order Number 54LS42DMQB 54LS42FMQB
DM54LS42J DM54LS42W DM74LS42M or DM74LS42N
See NS Package Number J16A M16A N16E or W16A
Logic Diagram
Features
Y Diode clamped inputs
Y Also for applications as 4-line-to-16-line decoders 3-
line-to-8-line decoders
Y All outputs are high for invalid input conditions
Y Alternate Military Aerospace device (54LS42) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Function Table
No BCD Inputs
Decimal Outputs
DCBA0 1 2 3 4 5 6 7 8 9
0 L L L L LHHHHHHHHH
1 L L LHHLHHHHHHHH
2 L LHLHHLHHHHHHH
3 L LHHHHHLHHHHHH
4 LHL LHHHHLHHHHH
5 LHLHHHHHHLHHHH
6 LHHLHHHHHHLHHH
7 LHHHHHHHHHHLHH
8 HL L LHHHHHHHHLH
9 HL LHHHHHHHHHHL
I
N
V
A
L
I
D
H L H L HHHHHHHHHH
H L HHHHHHHHHHHH
HHL LHHHHHHHHHH
HH L HHHHHHHHHHH
HHH L HHHHHHHHHH
HHHHHHHHHHHHHH
H e High Level
L e Low Level
C1995 National Semiconductor Corporation TL F 6365
TL F 6365 – 2
RRD-B30M105 Printed in U S A

1 Page



54LS42 pdf, ピン配列
Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL e 2 kX
CL e 15 pF
CL e 50 pF
Min Max Min Max
Units
tPHL
Propagation Delay Time
High to Low Level Output
A B C or D (2 Levels
of Logic) to Output
25
30 ns
tPHL
Propagation Delay Time
High to Low Level Output
A B C or D (3 Levels
of Logic) to Output
30
35 ns
tPLH
Propagation Delay Time
Low to High Level Output
A B C or D (2 Levels
of Logic) to Output
25
30 ns
tPLH
Propagation Delay Time
Low to High Level Output
A B C or D (3 Levels
of Logic) to Output
30
35 ns
3


3Pages


54LS42 電子部品, 半導体
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 54LS42FMQB or DM54LS42W
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
systems which (a) are intended for surgical implant
into the body or (b) support or sustain life and whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling can
be reasonably expected to result in a significant injury
to the user
2 A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system or to affect its safety or
effectiveness
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Corporation
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Arlington TX 76017
Tel 1(800) 272-9959
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National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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