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DM74161 の電気的特性と機能

DM74161のメーカーはNational Semiconductorです、この部品の機能は「Synchronous 4-Bit Counters」です。


製品の詳細 ( Datasheet PDF )

部品番号 DM74161
部品説明 Synchronous 4-Bit Counters
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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DM74161 Datasheet, DM74161 PDF,ピン配置, 機能
October 1992
DM54161 DM74161 DM74163
Synchronous 4-Bit Counters
General Description
These synchronous presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs The 161 and 163 are 4-bit binary counters The
carry output is decoded by means of a NOR gate thus pre-
venting spikes during the normal counting mode of opera-
tion Synchronous operation is provided by having all flip-
flops clocked simultaneously so that the outputs change co-
incident with each other when so instructed by the count-
enable inputs and internal gating This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform
These counters are fully programmable that is the outputs
may be preset to either level As presetting is synchronous
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable
input The clear function for the 161 is asynchronous and a
low level at the clear input sets all four of the flip-flop out-
puts low regardless of the levels of clock load or enable
inputs The clear function for the 163 is synchronous and a
low level at the clear input sets all four of the flip-flop out-
puts low after the next clock pulse regardless of the levels
of the enable inputs This synchronous clear allows the
count length to be modified easily as decoding the maxi-
mum count desired can be accomplished with one
external NAND gate The gate output is connected to the
clear input to synchronously clear the counter to all low out-
puts Low-to-high transitions at the clear input of the 163 are
also permissible regardless of the logic levels on the clock
enable or load inputs
The carry look-ahead circuitry provides for cascading coun-
ters for n-bit synchronous applications without additional
gating Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output Both count-
enable inputs (P and T) must be high to count and input T is
fed forward to enable the ripple carry output The ripple car-
ry output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the QA output This high-level overflow ripple carry pulse
can be used to enable successive cascaded stages High-
to-low-level transitions at the enable P or T inputs of the 161
through 163 may occur regardless of the logic level on the
clock
Features
Y Synchronously programmable
Y Internal look-ahead for fast counting
Y Carry output for n-bit cascading
Y Synchronous counting
Y Load control line
Y Diode-clamped inputs
Connection Diagram
Dual-In-Line Package
Order Number DM54161J DM54161W
DM74161N or DM74163N
See NS Package Number J16A N16E or W16A
TL F 6551 – 1
C1995 National Semiconductor Corporation TL F 6551
RRD-B30M105 Printed in U S A

1 Page





DM74161 pdf, ピン配列
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
Parameter
Conditions
Typ
Min
(Note 1)
IOS Short Circuit
VCC e Max
DM54
b20
Output Current
(Note 2)
DM74
b20
ICCH
Supply Current
with Outputs High
VCC e Max
(Note 3)
DM54
DM74
59
ICCL
Supply Current
with Outputs Low
VCC e Max
(Note 4)
DM54
DM74
63
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time
Note 3 ICCH is measured with the LOAD high then again with the LOAD low with all inputs high and all outputs open
Note 4 ICCL is measured with the CLOCK high then again with the CLOCK input low with all inputs low and all outputs open
Note 5 Applies to 163 which has synchronous clear inputs
Note 6 TA e 25 C and VCC e 5V
Max
b57
b57
85
94
91
101
Units
mA
mA
mA
Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
RL e 400X CL e 15 pF
Min Max
Units
fMAX
Maximum Clock
Frequency
25 MHz
tPLH
Propagation Delay Time
Clock to
Low to High Level Output
Ripple Carry
35 ns
tPHL
Propagation Delay Time
Clock to
High to Low Level Output
Ripple Carry
35 ns
tPLH
Propagation Delay Time
Clock
Low to High Level Output
(Load High) to Q
20 ns
tPHL
Propagation Delay Time
Clock
High to Low Level Output
(Load High) to Q
23 ns
tPLH
Propagation Delay Time
Clock
Low to High Level Output
(Load Low) to Q
25 ns
tPHL
Propagation Delay Time
Clock
High to Low Level Output
(Load Low) to Q
29 ns
tPLH Propagation Delay Time Enable T to
Low to High Level Output
Ripple Carry
16 ns
tPHL Propagation Delay Time Enable T to
High to Low Level Output
Ripple Carry
16 ns
tPHL
Propagation Delay Time
Clear (Note 7)
High to Low Level Output
to Q
38 ns
Note 7 Propagation delay for clearing is measured from the clear input for the 161 or from the clock input transition for the 163
3


3Pages


DM74161 電子部品, 半導体
Logic Diagrams (Continued)
161 163 Synchronous Binary Counters
Typical Clear Preset Count and Inhibit Sequences
(1) Clear outputs to zero
(2) Reset to binary twelve
(3) Count to thirteen fourteen fifteen zero one and two
(4) Inhibit
TL F 6551 – 5
6

6 Page



ページ 合計 : 10 ページ
 
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共有リンク

Link :


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