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PDF IRS2330D Data sheet ( Hoja de datos )

Número de pieza IRS2330D
Descripción 3-PHASE-BRIDGE DRIVER
Fabricantes International Rectifier 
Logotipo International Rectifier Logotipo



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IRS233(0,2)(D)(S&J)PbF
June 1 2011
IRS233(0,2)(D)(S & J)PbF
3-PHASE-BRIDGE DRIVER
Features
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Independent half-bridge drivers
Matched propagation delay for all channels
3.3 V logic compatible
Outputs out of phase with inputs
Cross-conduction prevention logic
Integrated Operational Amplifier
Integrated Bootstrap Diode function (IRS233(0,2)D)
RoHS Compliant
Product Summary
VOFFSET
600V max.
IO+/- 200 mA / 420 mA
VOUT
10 V – 20 V (233(0,2)(D))
ton/off (typ.)
500 ns
Deadtime (typ.)
2.0 us (IRS2330(D))
0.7 us (IRS2332(D))
Applications:
*Motor Control
*Air Conditioners/ Washing Machines
*General Purpose Inverters
*Micro/Mini Inverter Drives
Description
Packages
The IRS233(0,2)(D)(S & J) is a high voltage, high speed
power MOSFET and IGBT driver with three independent high
and low side referenced output channels. Proprietary HVIC
technology enables ruggedized monolithic construction.
Logic inputs are compatible with CMOS or LSTTL outputs,
down to 3.3 V logic. A ground-referenced operational
amplifier provides analog feedback of bridge current via an
external current sense resistor. A current trip function which
terminates all six outputs is also derived from this resistor.
An open drain FAULT signal indicates if an over-current or
undervoltage shutdown has occurred. The output drivers
feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are
matched to simplify use at high frequencies. The floating
channel can be used to drive N-channel power MOSFET
or IGBT in the high side configuration which operates up
to 600 volts.
28-Lead SOIC
44-Lead PLCC w/o 12 Leads
Typical Connection
Absolute Maximum Ratings
www.irf.com
1
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IRS2330D pdf
IRS233(0,2)(D)(S&J)PbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.
Symbol
SR+
SR-
Definition
Operational amplifier slew rate (+)
Operational amplifier slew rate (-)
Min Typ Max Units Test Conditions
5 10
2.4 3.2
V/µs
1 V input step
www.irf.com
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IRS2330D arduino
HIN1,2,3
A
B
LIN1, 2, 3
IRS233(0,2)(D)(S&J)PbF
ITRIP
FAULT
HO1, 2, 3
LO1, 2, 3
Figure 4: Input/output timing diagram
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within
IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a
minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power
switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is
automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified
by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals.
The deadtime circuitry of the IRS233(0,2)(D) is matched with respect to the high- and low-side outputs of a given channel;
additionally, the deadtimes of each of the three channels are matched.
www.irf.com
Figure 5: Illustration of deadtime
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