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PDF MCP3913 Data sheet ( Hoja de datos )
| Número de pieza | MCP3913 | |
| Descripción | 3V Six-Channel Analog Front End | |
| Fabricantes | Microchip | |
| Logotipo |  |
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MCP3913
3V Six-Channel Analog Front End
Features:
• Six Synchronous Sampling 24-bit Resolution
Delta-Sigma A/D Converters
• 94.5 dB SINAD, -107 dBc Total Harmonic
Distortion (THD) (up to 35th Harmonic), 112 dBFS
SFDR for Each Channel
• Enables 0.1% Typical Active Power Measurement
Error over a 10,000:1 Dynamic Range
• Advanced Security Features:
- 16-bit Cyclic Redundancy Check (CRC)
Checksum on All Communications for Secure
Data Transfers
- 16-bit CRC Checksum and Interrupt Alert for
Register Map Configuration
- Register Map lock with 8-bit Secure Key
• 2.7V-3.6V AVDD, DVDD
• Programmable Data Rate up to 125 ksps:
- 4 MHz Maximum Sampling Frequency
- 16 MHz Maximum Master Clock
• Oversampling Ratio up to 4096
• Ultra-Low Power Shutdown Mode with < 10 µA
• -122 dB Crosstalk between Channels
• Low Drift 1.2V Internal Voltage Reference:
9 ppm/°C
• Differential Voltage Reference Input Pins
• High Gain PGA on Each Channel (up to 32 V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Data Ready Pin for Easy
Synchronization
• Individual 24-bit Digital Offset and Gain Error
Correction for Each Channel
• High-Speed 20 MHz SPI Interface with Mode 0,0
and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication Time with Dedicated 16/32-bit
Modes
• Available in a 40-lead UQFN and 28-lead SSOP
Packages
• Extended Temperature Range: -40°C to +125°C
Description:
The MCP3913 is a 3V six-channel Analog Front End
(AFE), containing six synchronous sampling delta-
sigma, Analog-to-Digital Converters (ADC), six PGAs,
phase delay compensation block, low-drift internal
voltage reference, digital offset and gain error
calibration registers, and high-speed 20 MHz
SPI-compatible serial interface.
The MCP3913 ADCs are fully configurable, with
features such as: 16/24-bit resolution, Oversampling
Ratio (OSR) from 32 to 4096, gain from 1x to 32x,
independent Shutdown and Reset, dithering and auto-
zeroing. The communication is largely simplified with 8-
bit commands, including various continuous read/write
modes and 16/24/32-bit data formats that can be
accessed by the Direct Memory Access (DMA) of an
8/16- or 32-bit MCU, and with the separate data ready
pin that can directly be connected to an Interrupt
Request (IRQ) input of an MCU.
The MCP3913 includes advanced security features to
secure the communications and the configuration
settings, such as a CRC-16 checksum on both serial
data outputs and static register map configuration. It
also includes a register-map lock through an 8-bit
secure key to stop unwanted write commands from
processing.
The MCP3913 is capable of interfacing with a variety of
voltage and current sensors, including shunts, current
transformers, Rogowski coils and Hall-effect sensors.
Applications:
• Polyphase Energy Meters
• Energy Metering and Power Measurement
• Automotive
• Portable Instrumentation
• Medical and Power Monitoring
• Audio/Voice Recognition
2013 Microchip Technology Inc.
DS20005227A-page 1
1 page  
MCP3913
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V, MCLK = 4 MHz;
PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER<1:0> = 11; BOOST<1:0> = 10, VCM = 0V;
TA = -40°C to +125°C;VIN = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic
Sym.
Min. Typ. Max. Units
Conditions
Internal Voltage Reference
Tolerance
VREF
Temperature Coefficient
TCVREF
1.176 1.2 1.224
V VREFEXT = 0,
TA = +25°C only
— 9 — ppm/°C TA = -40°C to +125°C,
VREFEXT = 0,
VREFCAL<7:0> = 0x50
Output Impedance
ZOUTVREF
—
0.6
—
Internal Voltage Reference AIDDVREF — 54 —
Operating Current
k VREFEXT = 0
µA VREFEXT = 0,
SHUTDOWN<5:0> = 111111
Voltage Reference Input
Input Capacitance
— — 10
pF
Differential Input Voltage
Range (VREF+ – VREF-)
Absolute Voltage on
REFIN+ pin
VREF
VREF+
1.1 — 1.3
VREF- — VREF-
+ 1.1
+ 1.3
V VREFEXT = 1
V VREFEXT = 1
Absolute Voltage
REFIN- pin
Master Clock Input
VREF-
-0.1 — +0.1
V REFIN- should be connected to
AGND when VREFEXT = 0
Master Clock Input
Frequency Range
fMCLK
— — 20 MHz CLKEXT = 1, (Note 7)
Crystal Oscillator
Operating Frequency
Range
fXTAL
1 — 20 MHz CLKEXT = 0, (Note 7)
Analog Master Clock
Crystal Oscillator
Operating Current
AMCLK
— — 16 MHz (Note 7)
DIDDXTAL
—
80
—
µA CLKEXT = 0
Power Supply
Operating Voltage, Analog
Operating Voltage, Digital
Operating Current, Analog
(Note 2)
AVDD
DVDD
IDD,A
2.7 — 3.6
2.7 — 3.6
— 4.5
6
— 5.4
8
V
V
mA BOOST<1:0> = 00
mA BOOST<1:0> = 01
— 7.4 10
mA BOOST<1:0> = 10
— 12.9 17.5
mA BOOST<1:0> = 11
Note 1:
2:
3:
4:
5:
6:
7:
Dynamic Performance specified at -0.5 dB below the maximum differential input value,
VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz, VREF = 1.2V. See Section 4.0 “Terminology And Formulas” for definition.
This parameter is established by characterization and not 100% tested.
For these operating currents, the following configuration bit settings apply: SHUTDOWN<5:0> = 000000,
RESET<5:0> = 000000, VREFEXT = 0, CLKEXT = 0.
For these operating currents, the following configuration bit settings apply: SHUTDOWN<5:0> = 111111,
VREFEXT = 1, CLKEXT = 1.
Measured on one channel versus all others channels. The average of crosstalk performance over all channels
(see Figure 2-32 for individual channel performance).
Applies to all gains. Offset and gain errors depend on PGA gain setting, see typical performance curves for typical
performance.
Outside of this range, ADC accuracy is not specified. An extended input range of +/-2V can be applied continuously to
the part with no damage.
For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in
Table 5-2, as a function of the BOOST and PGA setting chosen. MCLK can take larger values as long as the prescaler
settings (PRE<1:0>) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
2013 Microchip Technology Inc.
DS20005227A-page 5
5 Page 
MCP3913
Note: Unless otherwise indicated, AVDD = 3V, DVDD = 3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels, VREFEXT = 0; CLKEXT = 1;
BOOST<1:0> = 10.
L
120
100
95
100
90
80
85
60 80
40
Dithering = Maximum
20
Dithering = Medium
Dithering = Minimum
Dithering = OFF
0
32 64 128 256 512 1024 2048 4096
Oversampling Ratio (OSR)
FIGURE 2-13:
SNR vs.OSR.
75
70
65
60
2
4
FIGURE 2-16:
Boost = 00
Boost = 11
Boost = 01
Boost = 10
6 8 10 12 14 16 18 20
MCLK Frequency (MHz)
SINAD vs. MCLK.
120
115
110
105
100
95
90 Dithering = Maximum
Dithering = Medium
85 Dithering = Minimum
Dithering = OFF
80
32 64 128 256 512 1024 2048 4096
Oversampling Ratio (OSR)
FIGURE 2-14:
SFDR vs. OSR.
100
95
90
85
80
75
70 Boost = 00
Boost = 11
65 Boost = 01
Boost = 10
60
2 4 6 8 10 12 14 16 18 20
MCLK Frequency (MHz)
FIGURE 2-17:
SNR vs. MCLK.
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
246
FIGURE 2-15:
Boost = 00
Boost = 01
Boost = 10
Boost = 11
8 10 12 14 16 18 20
MCLK Frequency (MHz)
THD vs. MCLK.
120
110
100
90
80
70
60
24
FIGURE 2-18:
Boost = 00
Boost = 11
Boost = 01
Boost = 10
6 8 10 12 14 16 18 20
MCLK Frequency (MHz)
SFDR vs. MCLK.
2013 Microchip Technology Inc.
DS20005227A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP3913.PDF ] | |
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