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PDF MR45V256A Data sheet ( 特性 )

部品番号 MR45V256A
部品説明 FeRAM
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MR45V256A Datasheet, MR45V256A PDF,ピン配置, 機能
MR45V256A
FEDR45V256A-01
Issue Date: Nov. 12, 2013
256k(32,768-Word 8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI
GENERAL DESCRIPTION
The MR45V256A is a nonvolatile 32,768-word x 8-bit ferroelectric random access memory (FeRAM) developed
in the ferroelectric process and silicon-gate CMOS technology. The MR45V256A is accessed using Serial
Peripheral Interface.Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required
to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as
those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and the
power consumption during a write can be reduced significantly.
The MR45V256A can be used in various applications, because the device is guaranteed for the write/read
tolerance of 1012 cycles per bit and the rewrite count can be extended significantly.
FEATURES
• 32,768-word 8-bit configuration (Serial Peripheral Interface : SPI)
• A single 3.3 V 0.3 V power supply
• Operating frequency:
• Read/write tolerance
15MHz
1012 cycles/bit
• Data retention
10 years
• Guaranteed operating temperature range
40 to 85C (Extended temperature version)
• Package options:
8-pin plastic SOP (P-SOP8-200-1.27-T2K )
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MR45V256A pdf, ピン配列
FEDR45V256A-01
MR45V256A
PIN DESCRIPTIONS
Pin Name
Description
Chip Select (input, negative logic)
CS# Latches an address by low input, activates the FeRAM, and enables a read or write
operation.
WP#
Write Protect( input , negative logic )
Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should
be fixed low or high in write-operations.
HOLD( input , negative logic )
HOLD#
Hold pin is used when the serial-communication suspended without disable the chip
select. When HOLD# is low ,the serial-output is in High-Z status and
serial-input/serial-clock are “Don’t Care” . CS# should be low in hold operation.
SCK
Serial Clock
Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on
the rising edge and output occur on the falling edge.
Serial input
SI
SI pins are serial input pins for Operation-code , addresses ,and data-inputs .
SO
VCC, VSS
Serial output
SO pins are serial output pins.
Power supply
Apply the specified voltage to VCC. Connect VSS to ground.
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3Pages


MR45V256A 電子部品, 半導体
FEDR45V256A-01
MR45V256A
Commands
WREN(Write Enable)
It is necessary to set Write Enable LatchWELbit before write-operation (WRITE and WRSR).
WREN command sets WEL bit.
CS#
WP# Fixed “H”
01234567
SCK
SI
SO
High-Z
WRDI(Write Disable)
WRDI command resets WEL bit.
CS#
WP# Fixed “H”
01234567
SCK
SI
SO
High-Z
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