PDF MR45V200A Data sheet ( Hoja de datos )

Número de pieza	MR45V200A
Descripción	FeRAM
Fabricantes	LAPIS
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No Preview Available ! MR45V200A FEDR45V200A-01 Issue Date: Jan. 31, 2014 2M(262,144-Word  8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI GENERAL DESCRIPTION The MR45V200A is a nonvolatile 262,144-word x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology. The MR45V200A is accessed using Serial Peripheral Interface.Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. The MR45V200A can be used in various applications, because the device is guaranteed for the write/read tolerance of 1012 cycles per bit and the rewrite count can be extended significantly. FEATURES • 262,144-word  8-bit configuration (Serial Peripheral Interface : SPI) • A single 2.7V to 3.6V power supply • Operating frequency: • Read/write tolerance 34MHz 1012 cycles/bit • Data retention 10 years • Guaranteed operating temperature range 40 to 85C (Extended temperature version) • Package options: 8-pin plastic DIP 1/17 1 page FEDR45V200A-01 MR45V200A RDSR(READ Status Register) The RDSR command allows to read data of status register. CS# WP# SCK SI SO Fixed “H” 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 High-Z 765432107 SRWD 0 0 0 BP1 BP0 WEL WIP SRWD WRSR(WRITE Status Register） WRSR command allows to write data to status register(SRWD,BP0,BP1). It is necessary to set Write Enable Latch（WEL）bit by WREN command before executing WRSR. CS# SCK SI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 76543210 SRWD X X X BP1 BP0 X X SO High-Z Note: WP#=Fix ”H” 5/17 5 Page FEDR45V200A-01 MR45V200A AC Characteristics (Read Cycle) Parameter Symbol Clock frequency CS# Active setup time CS# In-active setup-time CS# De-select time CS# Active hold time CS# In-active hold-time SCK High time SCK Low time SCK Rise time SCK Fall time Data Setup time Data Hold time SCK Low Hold time after HOLD# inactive SCK Low Hold time after HOLD# active SCK High Setup time before HOLD# active SCK High Setup time before HOLD# inactive Output disable time SCK Low to Output Valid time Output Hold time HOLD# High to Output Low impedance time HOLD# High to Output High impedance time Note: 1. tCH＋tCL≧1/fC 2. sample value fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH tCL tCLCH tCHCL tDVCH tCHDX tHHCH tHLCH tCHHL tCHHH tSHQZ tCLQV tCLQX tHHQX tHLQZ VCC=Max. to Min., Ta=Topr. MR45V200A Min. Max. Unit Note D.C. 10 10 10 10 10 13 13 ― ― 5 5 10 10 34 MHz ― ns ― ns ― ns ― ns ― ns ― ns 1 ― ns 1 50 ns 2 50 ns 2 ― ns ― ns ― ns ― ns 10 ― ns 10 ― ns ― 12 ns 2 ― 12 ns 0 ― ns ― 20 ns 2 ― 20 ns 2 11/17 11 Page

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Número de pieza	Descripción	Fabricantes
MR45V200A	FeRAM	LAPIS

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