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PDF MR44V064B Data sheet ( 特性 )

部品番号 MR44V064B
部品説明 FeRAM
メーカ LAPIS
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MR44V064B Datasheet, MR44V064B PDF,ピン配置, 機能
MR44V064B
64k(8,192-Word × 8-Bit) FeRAM (Ferroelectric Random Access Memory) I2C
FEDR44V064B-01
Issue Date: Jan. 08, 2016
GENERAL DESCRIPTION
The MR44V064B is a nonvolatile 8,192-word x 8-bit ferroelectric random access memory (FeRAM) developed
in the ferroelectric process and silicon-gate CMOS technology. The MR44V064B is accessed using Two-wire
Serial Interface ( I2C BUS ).Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup
required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks,
such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and
the power consumption during a write can be reduced significantly.
The MR44V064B can be used in various applications, because the device is guaranteed for the write/read
tolerance of 1012 cycles per bit and the rewrite count can be extended significantly.
FEATURES
• 8,192-word × 8-bit configuration I2C BUS Interface
• A single 3.3 V typ (1.8V to 3.6V) power supply
• Operating frequency:
3.4MHz(Max) HS-mode
• Read/write tolerance
1MHz(Max) F/S-mode Plus
1012 cycles/bit
• Data retention
10 years
• Guaranteed operating temperature range
40 to 85°C (Extended temperature version)
• Package options:
8-pin plastic SOP (P-SOP8-200-1.27-T2K)
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MR44V064B pdf, ピン配列
FEDR44V064B-01
MR44V064B
I2C BUS
The MR44V064B employs a bi-directional two-wire I2C BUS interface, works as a slave device.
An example of I2C interface system with MR44V064B
SCL
SDA
SCL SDA
I2C BUS
master
SCL SDA
MR44V064B
(slave)
A2 A1 A0
000
SCL SDA
MR44V064B
(slave)
A2 A1 A0
001
Pull-up
resistor
I2C BUS COMUNICATION
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always
8bit long, acknowledge is always required after each byte. I2C BUS carries out data transmission with plural
devices connected by 2 communication lines of serial data ( SDA ) and serial clock ( SCL ).
SCL
1-7 8 9
SDA
START ADDRESS
condition
R/W
ACK
1-7 8 9
DATA
ACK
1-7 8 9
DATA
ACK
STOP
condition
START CONDITION
Before executing each command, start condition ( start bit ) where SDA goes from “HIGH” down to “LOW”
when SCL is “HIGH” is necessary. MR44V064B always detects whether SDA and SCL are in start condition
( start bit ) or not, therefore, unless this condition is satisfied, any command is executed.
STOP CONDITION
Each command can be ended by SDA rising from “LOW” to “HIGH” when stop condition ( stop bit ),
namely,SCL is “HIGH”.
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3Pages


MR44V064B 電子部品, 半導体
FEDR44V064B-01
MR44V064B
RANDOM READ CYCLE
Random read cycle is a command to read data by designating address.
start condition
slave address with LSB is 0 (write)
1st and 2nd word address
start condition
slave address with LSB is 1 (read)
read out byte of data.
ACK to “H”
stop condition
S
T
A
R
T
Slave address
W
R
I
T
E
1 0 1 0 A2 A1 A0
1st WORD address
W
000A
12
W
A
8
2nd WORD address
WW
AA
70
S
T
A
R
T
Slave address
R
E
A
D
1 0 1 0 A2 A1 A0
D
7
AAA
CCC
KKK
A
C
K
Read data
S
T
O
P
D
0
N
A
C
K
SEQUENTIAL READ CYCLE
When ACK signal “L” after D0 is detected, and stop condition is not sent from master side, the next
address data can be read in succession.
S
T
A
R
T
Slave address
W
R
I
T
E
1 0 1 0 A2 A1 A0
1st WORD address
W
000A
12
W
A
8
2nd WORD address
WW
AA
70
S
T
A
R
T
Slave address
R
E
A
D
1 0 1 0 A2 A1 A0
AAA
CCC
KKK
A
C
K
DD
07
A
C
K
Read data
S
T
O
P
D
0
N
DA
C7
K
CURRENT ADDRESS READ CYCLE
Current address read cycle is a command to read data of internal address register without designating address.
When the last read or write address is (n)-th address just before current read cycle, the current address read
command outputs data of (n+1)-th address. The previous read or write sequence should be complete up to stop
condition.
S
T
A
R
T
Slave address
R
E
A
D
Read data
S
T
O
P
1 0 1 0 A2 A1 A0
D7
D0
AN
CA
KC
K
CURRENT ADDRESS READ CYCLE ( HS-MODE )
The MR44V064B support a 3.4MHz high speed mode. When HS-mode operation is needed, the HS-mode
command is required before any command. After the HS-mode command is issued, MR44V064B will be the
HS-mode, until stop condition is issued.
S
T
A
R
T
HS-mode command
0 0 0 0 1XXX
S
T
A
R
T
Slave address
R
E
A
D
1 0 1 0 A2 A1 A0
D7
NA
AC
CK
K
Read data
S
T
O
P
D0
N
A
C
K
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