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PDF 74LVC14A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC14A | |
| Descripción | Hex inverting Schmitt trigger | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74LVC14A
Hex inverting Schmitt trigger with 5 V tolerant input
Rev. 5 — 23 December 2011
Product data sheet
1. General description
The 74LVC14A provides six inverting buffers with Schmitt trigger input. It is capable of
transforming slowly-changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device as a translator in mixed 3.3 V and 5 V applications.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
5 V tolerant input for interfacing with 5 V logic
CMOS low-power consumption
Direct interface with TTL levels
Unlimited input rise and fall times
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Wave and pulse shapers for highly noisy environments
Astable multivibrators
Monostable multivibrators
1 page  
NXP Semiconductors
74LVC14A
Hex inverting Schmitt trigger with 5 V tolerant input
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
Min Typ[1] Max
VOH HIGH-level VI = VT+ or VT
output voltage
IO = 100 A;
VCC = 1.65 V to 3.6 V
VCC 0.2 -
-
IO = 4 mA; VCC = 1.65 V
1.2 - -
IO = 8 mA; VCC = 2.3 V
1.8 - -
IO = 12 mA; VCC = 2.7 V
2.2 - -
IO = 18 mA; VCC = 3.0 V
2.4 - -
IO = 24 mA; VCC = 3.0 V
2.2 - -
VOL LOW-level VI = VT+ or VT
voltage output
IO = 100 A; VCC = 1.65 V to 3.6 V -
- 0.2
IO = 4 mA; VCC = 1.65 V
- - 0.45
IO = 8 mA; VCC = 2.3 V
- - 0.6
IO = 12 mA; VCC = 2.7 V
- - 0.4
IO = 24 mA; VCC = 3.0 V
- - 0.55
II
input leakage VCC = 3.6 V; VI = 5.5 V or GND
-
current
0.1 5
ICC
ICC
CI
supply current
additional
supply current
input
capacitance
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
per input pin; VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
VCC = 0 V to 3.6 V; VI = GND to VCC
-
-
-
0.1 10
5 500
4.0 -
40 C to +125 C Unit
Min Max
VCC 0.3 -
1.05 -
1.65 -
2.05 -
2.25 -
2.0 -
V
V
V
V
V
V
- 0.3 V
- 0.65 V
- 0.8 V
- 0.6 V
- 0.8 V
- 20 A
- 40 A
- 5000 A
- - pF
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
40 C to +85 C
Min Typ[1] Max
tpd propagation delay nA to nY; see Figure 6
[2]
VCC = 1.2 V
- 16 -
VCC = 1.65 V to 1.95 V
1.0 6.1 12.7
VCC = 2.3 V to 2.7 V
1.5 3.5 7.8
VCC = 2.7 V
1.5 3.6 7.5
tsk(o)
output skew time
VCC = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V
1.0 3.2 6.4
[3] -
- 1.0
40 C to +125 C Unit
Min Max
- - ns
1.0 14.7 ns
1.5 10.0 ns
1.5 9.5 ns
1.0 8.0 ns
- 1.5 ns
74LVC14A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 23 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 18
5 Page 
NXP Semiconductors
74LVC14A
Hex inverting Schmitt trigger with 5 V tolerant input
16. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
y
Z
14
D
pin 1 index
1
e
EA
X
c
HE
vM A
8
A2
A1
7
bp
wM
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
UNIT max. A1 A2 A3 bp
c D(1) E(1) e
HE
L
Lp
Q
v
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
inches
0.069
0.010
0.004
0.057
0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.244
0.228
0.041
0.039
0.016
0.028
0.024
0.01
w y Z (1)
0.25 0.1
0.7
0.3
0.01
0.004
0.028
0.012
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE
VERSION
SOT108-1
IEC
076E06
REFERENCES
JEDEC
JEITA
MS-012
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 12. Package outline SOT108-1 (SO14)
74LVC14A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 23 December 2011
© NXP B.V. 2011. All rights reserved.
11 of 18
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 74LVC14A.PDF ] | |
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