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PDF AT24C64D Data sheet ( Hoja de datos )
| Número de pieza | AT24C64D | |
| Descripción | I2C-Compatible (2-Wire) Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT24C64D
I2C-Compatible (2-Wire) Serial EEPROM
64-Kbit (8,192 x 8)
DATASHEET
Features
Low-voltage and Standard-voltage Operation
̶ VCC = 1.7V to 5.5V
Internally Organized as 8,192 x 8 (64K)
I2C-compatible (2-Wire) Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility
Write Protect Pin for Hardware Protection
32-byte Page Write Mode
̶ Partial Page Writes Allowed
Self-timed Write Cycle (5ms Max)
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
Lead-free/Halogen-free Devices Available
Green Package Options (Pb/Halide-free/RoHS Compliant)
̶ 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 8-ball
VFBGA, and 4-ball/5-ball/6-ball WLCSP Packages
Die Sale Options: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT24C64D provides 65,536-bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 8,192 words of 8 bits
each. The device’s cascading feature allows up to eight devices to share a
common 2-wire bus. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operation are
essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead
TSSOP, 8-pad UDFN, 8-pad XDFN, 8-ball VFBGA, and 4-ball/5-ball/6-ball
WLCSP packages. In addition, this device operates from 1.7V to 5.5V.
Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015
1 page  
5.3 AC Characteristics
Table 5-3. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = 1.7V to 5.5V, CL = 100pF (unless
otherwise noted). Test conditions are listed in Note 2.
1.7V
2.5V, 5.0V
Symbol
Parameter
Min Max Min Max
Units
fSCL
tLOW
tHIGH
tI
tAA
tBUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
Time the bus must be free before a new transmission
can start(1)
1300
600
50
400
100
900
1300
1000
400
400
50
50 550
500
kHz
ns
ns
ns
ns
ns
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode, 3.3V
600 250
ns
600 250
ns
00
ns
100 100
ns
300 300 ns
300 100 ns
600 250
ns
50 50
ns
5 5 ms
1,000,000
Write Cycles
Notes: 1. This parameter is ensured by characterization and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3kΩ (2.5V, 5.5V), 10kΩ (1.7V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤ 50ns
Input and output timing reference voltages: 0.5 x VCC
AT24C64D [DATASHEET]
Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015
5
5 Page 
9. Read Operations
Read operations are initiated the same way as Write operations with the exception that the Read/Write select bit
in the device address word is set to one. There are three Read operations:
Current Address Read
Random Address Read
Sequential Read
Current Address Read: The internal data word address counter maintains the last address accessed during
the last Read or Write operation, incremented by one. This address stays valid between operations as long as
the chip power is maintained. The address roll-over during read is from the last byte of the last memory page, to
the first byte of the first page.
Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an
input zero but does generate a Stop condition.
Figure 9-1. Current Address Read
S
T
A
R Device
T Address
SDA Line
M
S
B
R
E
A
D
RA
/C
WK
Data
S
T
O
P
N
O
A
C
K
Random Read: A Random Read requires a dummy Byte Write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another Start condition. The microcontroller now initiates a Current Address
Read by sending a device address with the Read/Write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with a zero but does
generate a Stop condition.
Figure 9-2. Random Read
SDA LINE
S
T
A
R Device
T Address
M
S
B
W
R
I
T First Word
E Address
Second Word
Address
S
T
A
R Device
T Address
RA
/C
WK
A
C
K
LA
SC
BK
R
E
A
D
RA
/C
WK
Note: * = Don’t care bit.
Dummy Write
Data (n)
S
T
O
P
N
O
A
C
K
AT24C64D [DATASHEET]
Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AT24C64D.PDF ] | |
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