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PDF IS46TR81280ED Data sheet ( Hoja de datos )
| Número de pieza | IS46TR81280ED | |
| Descripción | 1Gb DDR3 SDRAM | |
| Fabricantes | ISSI | |
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IS43/46TR16640ED
IS43/46TR81280ED
128MX8, 64MX16 1Gb DDR3 SDRAM WITH ECC
FEATURES
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
High speed data transfer rates with system
frequency up to 800 MHz
8 internal banks for concurrent operation
8n-bit pre-fetch architecture
Programmable CAS Latency
Programmable Additive Latency: 0, CL-1,CL-2
Programmable CAS WRITE latency (CWL) based
on tCK
Programmable Burst Length: 4 and 8
Programmable Burst Sequence: Sequential or
Interleave
BL switch on the fly
Auto Self Refresh(ASR)
Self Refresh Temperature(SRT)
ECC
Single bit error correction (per 64-bits)
Restrictions on Burst Length and Data Mask
OPTIONS
Configuration:
128Mx8
64Mx16
Package:
96-ball FBGA (9mm x 13mm) for x16
78-ball FBGA (8mm x 10.5mm) for x8
Preliminary Information
AUGUST 2016
Refresh Interval:
7.8 μs (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 μs (8192 cycles/32 ms) Tc= 85°C to 105°C
1.95 μs (8192 cycles/16ms)Tc=105°C to 125°C
Partial Array Self Refresh
Asynchronous RESET pin
TDQS (Termination Data Strobe) supported (x8
only)
OCD (Off-Chip Driver Impedance Adjustment)
Dynamic ODT (On-Die Termination)
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )
Write Leveling
Operating temperature:
Automotive, A1 (TC = -40°C to +95°C)
Automotive, A2 (TC = -40°C to +105°C)
Automotive, A3 (TC= -40°C to +125°C)
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Page size
Auto Precharge Addressing
BL switch on the fly
128Mx8
A0-A13
A0-A9
BA0-2
1KB
A10/AP
A12/BC#
64Mx16
A0-A12
A0-A9
BA0-2
2KB
A10/AP
A12/BC#
SPEED BIN
Speed Option
JEDEC Speed Grade
CL-nRCD-nRP
tRCD,tRP(min)
15H
DDR3-1333H
9-9-9
13.5
125K
DDR3-1600K
11-11-11
13.75
Units
tCK
ns
Note: Faster speed options may be backward compatible to slower speed options. Refer to timing tables (8.3)
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 0B
08/08/2016
1
1 page  
IS43/46TR16640ED
IS43/46TR81280ED
2. FUNCTION DESCRIPTION
2.1 Simplified State Diagram
Power
applied
Power
On
Reset
Procedure
From
Any state RESET
Initialization
MRS,MPR,
Write
Leveling
ZQCL
ZQ
Calibration
ZQCL
ZQCS
Idle
SRE
SRX
REF
Self
Refresh
Refreshing
Write
Active
Power
Down
PDX
PDE
ACT
PDE
PDX
Activating
Writing
Write
Bank
Active
Read
Write A Read A
Read
Write
Precharge
Power
Down
Reading
Read
Write A
Writing
Write A Read A
PRE,PREA
PRE,PREA PRE,PREA
Read A
Reading
Abbreviation
ACT
PRE
PREA
MRS
REF
ZQCL
Function
Active
Precharge
Precharge All
Mode Register Set
Refresh
ZQ Calibration Long
Abbreviation
Read
Read A
Write
Write A
RESET
ZQCS
Precharging
Function
RD, RDS4, RDS8
RDA, RDAS4, RDAS8
WR, WRS4, WRS8
WRA, WRAS4, WRAS8
Start RESET Procedure
ZQ Calibration Short
Automatic
Sequence
Command
Sequence
Abbreviation
PDE
PDX
SRE
SRX
MPR
Function
Enter Power-down
Exit Power-down
Self-Refresh entry
Self-Refresh exit
Multi-Purpose Register
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 0B
08/08/2016
5
5 Page 
IS43/46TR16640ED
IS43/46TR81280ED
Write command via A12/BC#. Configuartion of BL4 or usage of BC4 may restrict the ECC Functionality. Please refer to
ECC Feature.
Burst
Length
READ/
WRITE
Starting
Column
ADDRESS
(A2,A1,A0)
burst type = Sequential
(decimal)
A3 = 0
burst type = Interleaved
(decimal)
A3 = 1
Notes
0 0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
1, 2, 3, 6
1 1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T
1, 2, 3, 6
10 2,3,0,1,T,T,T,T
2,3,0,1,T,T,T,T
1, 2, 3, 6
11 3,0,1,2,T,T,T,T
READ
4
100
4,5,6,7,T,T,T,T
Chop
101 5,6,7,4,T,T,T,T
3,2,1,0,T,T,T,T
4,5,6,7,T,T,T,T
5,4,7,6,T,T,T,T
1, 2, 3, 6
1, 2, 3, 6
1, 2, 3, 6
110 6,7,4,5,T,T,T,T
6,7,4,5,T,T,T,T
1, 2, 3, 6
111 7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
1, 2, 3, 6
WRITE
0,V,V
1,V,V
0,1,2,3,X,X,X,X
4,5,6,7,X,X,X,X
0,1,2,3,X,X,X,X
4,5,6,7,X,X,X,X
1, 2, 4, 5, 6
1, 2, 4, 5, 6
0 0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2
1 1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
2
10 2,3,0,1,6,7,4,5
2,3,0,1,6,7,4,5
2
8 READ
11
100
3,0,1,2,7,4,5,6
4,5,6,7,0,1,2,3
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
2
2
101 5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
2
110 6,7,4,5,2,3,0,1
6,7,4,5,2,3,0,1
2
111 7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
2
WRITE
V,V,V
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2, 4
Notes:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means
that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal
write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR
and tWTR will not be pulled in by two clocks.
2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Don’t Care.
6. Use of this burst length may restrict ECC functionality
2.3.2.2 CAS Latency
The CAS Latency is defined by MR0 (bits A9-A11) as shown in Figure 2.3.2. CAS Latency is the delay, in clock cycles,
between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM does not support
any half-clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL
+ CL. For more information on the supported CL and AL settings based on the operating clock frequency, refer to
“Standard Speed Bins”.
2.3.2.3 Test Mode
The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values shown in Figure
2.3.2. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only used by the DRAM Manufacturer
and should NOT be used. No operations or functionality is specified if A7 = 1.
2.3.2.4 DLL Reset
The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset function has been
issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any time that the DLL reset function is
used, tDLLK must be met before any functions that require the DLL can be used (i.e., Read commands or ODT
synchronous operations).
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 0B
08/08/2016
11
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| PDF Descargar | [ Datasheet IS46TR81280ED.PDF ] | |
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