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IS43TR81280ED の電気的特性と機能

IS43TR81280EDのメーカーはISSIです、この部品の機能は「1Gb DDR3 SDRAM」です。


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部品番号 IS43TR81280ED
部品説明 1Gb DDR3 SDRAM
メーカ ISSI
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IS43TR81280ED Datasheet, IS43TR81280ED PDF,ピン配置, 機能
IS43/46TR16640ED
IS43/46TR81280ED
128MX8, 64MX16 1Gb DDR3 SDRAM WITH ECC
FEATURES
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
High speed data transfer rates with system
frequency up to 800 MHz
8 internal banks for concurrent operation
8n-bit pre-fetch architecture
Programmable CAS Latency
Programmable Additive Latency: 0, CL-1,CL-2
Programmable CAS WRITE latency (CWL) based
on tCK
Programmable Burst Length: 4 and 8
Programmable Burst Sequence: Sequential or
Interleave
BL switch on the fly
Auto Self Refresh(ASR)
Self Refresh Temperature(SRT)
ECC
Single bit error correction (per 64-bits)
Restrictions on Burst Length and Data Mask
OPTIONS
Configuration:
128Mx8
64Mx16
Package:
96-ball FBGA (9mm x 13mm) for x16
78-ball FBGA (8mm x 10.5mm) for x8
Preliminary Information
AUGUST 2016
Refresh Interval:
7.8 μs (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 μs (8192 cycles/32 ms) Tc= 85°C to 105°C
1.95 μs (8192 cycles/16ms)Tc=105°C to 125°C
Partial Array Self Refresh
Asynchronous RESET pin
TDQS (Termination Data Strobe) supported (x8
only)
OCD (Off-Chip Driver Impedance Adjustment)
Dynamic ODT (On-Die Termination)
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )
Write Leveling
Operating temperature:
Automotive, A1 (TC = -40°C to +95°C)
Automotive, A2 (TC = -40°C to +105°C)
Automotive, A3 (TC= -40°C to +125°C)
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Page size
Auto Precharge Addressing
BL switch on the fly
128Mx8
A0-A13
A0-A9
BA0-2
1KB
A10/AP
A12/BC#
64Mx16
A0-A12
A0-A9
BA0-2
2KB
A10/AP
A12/BC#
SPEED BIN
Speed Option
JEDEC Speed Grade
CL-nRCD-nRP
tRCD,tRP(min)
15H
DDR3-1333H
9-9-9
13.5
125K
DDR3-1600K
11-11-11
13.75
Units
tCK
ns
Note: Faster speed options may be backward compatible to slower speed options. Refer to timing tables (8.3)
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. www.issi.com
Rev. 0B
08/08/2016
1

1 Page





IS43TR81280ED pdf, ピン配列
IS43/46TR16640ED
IS43/46TR81280ED
1.3 Pinout Description - JEDEC Standard
Symbol
Type
Function
CK, CK#
CKE
CS#
ODT
RAS#. CAS#.
WE#
DM, (DMU),
(DML)
BA0 - BA2
A0 - A13
A10 / AP
A12 / BC#
RESET#
DQ(DQL, DQU)
Input
Input
Input
Input
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK#.
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the
power on and initialization sequence, they must be maintained during all operations (including
Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK#, ODT and CKE, are disabled during power-down. Input buffers, excluding
CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for external
Rank selection on systems with multiple Ranks. CS# is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3
SDRAM. When enabled, ODT is only applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU,
and DML signal. The ODT pin will be ignored if MR1 and MR2 are programmed to disable RTT.
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered.
Input
Input
Input
Input
Input
Input
Input / Output
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. For x8 device, the function of DM or TDQS/TDQS# is enabled by Mode Register
A11 setting in MR1.
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write, or Precharge
command is being applied. Bank address also determines which mode register is to be accessed
during a MRS cycle.
Address Inputs: Provide the row address for Active commands and the column address for Read/
Write commands to select one location out of the memory array in the respective bank. (A10/AP
and A12/BC# have additional functions; see below). The address inputs also provide the op-code
during Mode Register Set commands.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by bank addresses.
Burst Chop: A12 / BC# is sampled during Read and Write commands to determine if burst chop
(on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth
table for details.
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when
RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail- to-
rail signal with DC high and low at 80% and 20% of VDD, i.e., 1.20V for DC high and 0.30V for
DC low.
Data Input/ Output: Bi-directional data bus.
DQS,
DQS#, DQSU,
DQSU#, DQSL,
DQSL#
TDQS, TDQS#
NC
Input / Output
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered
in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to
the data on DQU0-DQU7. The data strobes DQS, DQSL, and DQSU are paired with differential
signals DQS#, DQSL#, and DQSU#, respectively, to provide differential pair signaling to the
system during reads and writes. DDR3 SDRAM supports differential data strobe only and does
not support single-ended.
Termination Data Strobe: TDQS/TDQS# is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function
on TDQS/TDQS# that is applied to DQS/DQS#. When disabled via mode register A11 = 0 in
MR1, DM/TDQS will provide the data mask function and TDQS# is not used. x16 DRAMs must
disable the TDQS function via mode register A11 = 0 in MR1.
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 1.5 V +/- 0.075 V
Integrated Silicon Solution, Inc. www.issi.com
Rev. 0B
08/08/2016
3


3Pages


IS43TR81280ED 電子部品, 半導体
IS43/46TR16640ED
IS43/46TR81280ED
2.2 RESET and Initialization Procedure
2.2.1 Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined).
RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled Low” anytime before
RESET# being de-asserted (min. time 10 ns). The power voltage ramp time between 300mV to VDD(min) must be
no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts.
OR
VDD and VDDQ are driven from a single power converter output, AND
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to
0.95 V max once power ramp is finished, AND
Vref tracks VDDQ/2.
Apply VDD without any slope reversal before or at the same time as VDDQ.
Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM will
start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE goes
active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also, a NOP or
Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE is
registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is
finished, including expiration of tDLLK and tZQinit.
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is asserted. Further,
the SDRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered
HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is
registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled
in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the
power up initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS
command to load mode register. (tXPR=max (tXS ; 5 x tCK)
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command,
provide "Low" to A0, "High" to BA0 and "Low" to BA1 BA2).
Integrated Silicon Solution, Inc. www.issi.com
Rev. 0B
08/08/2016
6

6 Page



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部品番号部品説明メーカ
IS43TR81280ED

1Gb DDR3 SDRAM

ISSI
ISSI


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