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IS42SM32100D の電気的特性と機能

IS42SM32100DのメーカーはISSIです、この部品の機能は「512K x 32Bits x 2Banks Low Power Synchronous DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS42SM32100D
部品説明 512K x 32Bits x 2Banks Low Power Synchronous DRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS42SM32100D Datasheet, IS42SM32100D PDF,ピン配置, 機能
IS42/45SM/RM/VM32100D
512K x 32Bits x 2Banks Low Power Synchronous DRAM
Description
These IS42SM/RM/VM32100D are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32
bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.3V, 2.5V, 1.8V power supply.
Auto refresh and self refresh.
All pins are compatible with LVCMOS interface.
4K refresh cycle / 64ms.
Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
Programmable CAS Latency : 2,3 clocks.
All inputs and outputs referenced to the positive edge of the
system clock.
Data mask function by DQM.
Internal dual banks operation.
Burst Read Single Write operation.
Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
Programmable Driver Strength Control
- Full Strength or 1/2, 1/4, of Full Strength
Deep Power Down Mode.
Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. A | November 2015
www.issi.com - [email protected]
1

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IS42SM32100D pdf, ピン配列
IS42/45SM/RM/VM32100D
Table2: Pin Descriptions
Pin
Pin Name
CLK System Clock
CKE Clock Enable
/CS Chip Select
BA Bank Address
A0~A10
/RAS, /CAS, /WE
DQM0~DQM3
DQ0~DQ31
VDD/VSS
VDDQ/VSSQ
NC
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
Descriptions
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
Row Address
Column Address
Auto Precharge
: RA0~RA10
: CA0~CA7
: A10
RAS, CAS and WE define the operation.
Refer function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Data input/output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
Rev. A | November 2015
www.issi.com - [email protected]
3


3Pages


IS42SM32100D 電子部品, 半導体
IS42/45SM/RM/VM32100D
Figure4: Mode Register Definition
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
11 10
9
8
7
0 0 WB 0 0
6543
CAS Latency
BT
210
Burst Length
Mode Register (Mx)
M9 Write Burst Mode
0 Burst Read and Burst Write
1 Burst Read and Single Write
M6 M5 M4 CAS Latency
000
Reserved
001
Reserved
010
2
011
3
100
Reserved
101
Reserved
110
Reserved
111
Reserved
M3 Burst Type
0 Sequential
1 Interleave
Note: M11(BA) must be set to “0” to select Mode Register (vs. the Extended Mode Register)
M2 M1 M0
Burst Length
M3 = 0
M3 = 1
000
1
1
001
2
2
010
4
4
011
8
8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
Table 3: Burst Definition
Burst
Length
Starting Column
Address
A2 A1 A0
Order of Access Within a Burst
Sequential
Interleaved
2
0 0-1
1 1-0
0-1
1-0
00
0-1-2-3
0-1-2-3
01
1-2-3-0
1-0-3-2
4
10
2-3-0-1
2-3-0-1
11
3-0-1-2
3-2-1-0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
8
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full
Page
n=A0-7
(Location 0-256)
Cn, Cn+1. Cn+2,
Cn+3, Cn+4…
…Cn-1, Cn...
Not Supported
Note :
1. For full-page accesses: y = 256
2. For a burst length of two, A1-A7 select the block-
of-two burst; A0 selects the starting column within the
block.
3. For a burst length of four, A2-A7 select the block-
of-four burst; A0-A1 select the starting column within
the block.
4. For a burst length of eight, A3-A7 select the
block-of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-A7
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3 is
ignored.
Rev. A | November 2015
www.issi.com - [email protected]
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