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CY7C1910BV18 の電気的特性と機能

CY7C1910BV18のメーカーはCypress Semiconductorです、この部品の機能は「1.8V Synchronous Pipelined SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY7C1910BV18
部品説明 1.8V Synchronous Pipelined SRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY7C1910BV18 Datasheet, CY7C1910BV18 PDF,ピン配置, 機能
CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18
18-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Features
Separate independent read and write data ports
Supports concurrent transactions
250 MHz clock for high bandwidth
2-word burst on all accesses
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 500 MHz) at 250 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
Available in x8, x9, x18, and x36 configurations
Full data coherency, providing most current data
Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310BV18 – 2M x 8
CY7C1910BV18 – 2M x 9
CY7C1312BV18 – 1M x 18
CY7C1314BV18 – 512K x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
250 MHz
250
735
735
800
900
Functional Description
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has data outputs to
support read operations and the write port has data inputs to
support write operations. QDR-II architecture has separate data
inputs and data outputs to completely eliminate the need to
“turn-around” the data bus required with common IO devices.
Access to each port is accomplished through a common address
bus. The read address is latched on the rising edge of the K clock
and the write address is latched on the rising edge of the K clock.
Accesses to the QDR-II read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are provided with DDR interfaces. Each
address location is associated with two 8-bit words
(CY7C1310BV18), 9-bit words (CY7C1910BV18), 18-bit words
(CY7C1312BV18), or 36-bit words (CY7C1314BV18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K and C and C), memory bandwidth is maximized
while simplifying system design by eliminating bus
“turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
200 MHz
200
630
630
675
750
167 MHz
167
550
550
600
650
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05619 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 2, 2008
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CY7C1910BV18 pdf, ピン配列
Logic Block Diagram (CY7C1312BV18)
CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18
D[17:0]
18
A(18:0) 19
Address
Register
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Address
Register
19 A(18:0)
Read Data Reg.
36
18
18
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
Q[17:0]
Logic Block Diagram (CY7C1314BV18)
D[35:0]
36
A(17:0) 18
Address
Register
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Address
Register
18 A(17:0)
Read Data Reg.
72
36
36
Control
Logic
RPS
C
C
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
Q[35:0]
Document #: 38-05619 Rev. *F
Page 3 of 29
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CY7C1910BV18 電子部品, 半導体
CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
WPS
NWS0,
NWS1
Input- Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
Synchronous CY7C1310BV18 - D[7:0]
CY7C1910BV18 - D[8:0]
CY7C1312BV18 - D[17:0]
CY7C1314BV18 - D[35:0]
Input- Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
Nibble Write Select 0, 1 Active LOW (CY7C1310BV18 Only). Sampled on the rising edge of the K
and K clocks during Write operations. Used to select which nibble is written into the device during the
current portion of the Write operations.Nibbles not written remain unaltered. NWS0 controls D[3:0] and
NWS1 controls D[7:4].
All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input- Byte Write Select 0, 1, 2 and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1910BV18 BWS0 controls D[8:0]
CY7C1312BV18 BWS0 controls D[8:0], BWS1 controls D[17:9].
CY7C1314BV18 BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A Input- Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write address) clocks during
Synchronous active read and write operations. These address inputs are multiplexed for both read and write operations.
Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1310BV18, 2M x 9 (2
arrays each of 1M x 9) for CY7C1910BV18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1312BV18
and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314BV18. Therefore, only 20 address inputs are
needed to access the entire memory array of CY7C1310BV18 and CY7C1910BV18, 19 address inputs
for CY7C1312BV18 and 18 address inputs for CY7C1314BV18. These inputs are ignored when the
appropriate port is deselected.
Q[x:0]
RPS
Outputs- Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1310BV18 Q[7:0]
CY7C1910BV18 Q[8:0]
CY7C1312BV18 Q[17:0]
CY7C1314BV18 Q[35:0]
Input- Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of two sequential transfers.
C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 9 for further details.
C Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 9 for further details.
K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
Document #: 38-05619 Rev. *F
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部品番号部品説明メーカ
CY7C1910BV18

1.8V Synchronous Pipelined SRAM

Cypress Semiconductor
Cypress Semiconductor


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