DP7269 データシート ( Dual Digital Potentiometers )

部品番号

DP7269

部品説明

Dual Digital Potentiometers

メーカ

COPAL ELECTRONICS

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Dual Digital Potentiometers

(DP) with 256 Taps and 2-wire Interface

DP7269

FEATURES

Four linear taper digital potentiometers

256 resistor taps per potentiometer

End to end resistance 50k or 100k

Potentiometer control and memory access via

2-wire interface (I2C like)

Low wiper resistance, typically 100

Nonvolatile memory storage for up to four

wiper settings for each potentiometer

Automatic recall of saved wiper settings at

power up

2.5 to 6.0 volt operation

Standby current less than 1µA

1,000,000 nonvolatile WRITE cycles

100 year nonvolatile memory data retention

24-lead SOIC and TSSOP packages

Industrial temperature range

For Ordering Information details, see page 15.

PIN CONFIGURATION

SOIC (W)

TSSOP (Y)

NC 1

A0 2

NC 3

NC 4

NC 5

NC 6

VCC 7

RLO 8

RHO 9

RWO 10

A2 11

¯W¯P¯ 12

24 A3

23 SCL

22 NC

21 NC

20 NC

19 NC

18 GND

17 RW1

16 RH1

15 RL1

14 A1

13 SDA

DESCRIPTION

The DP7269 is two digital potentiometers

(DPs) integrated with control logic and 18 bytes

of NVRAM memory. Each DP consists of a

series of resistive elements connected between two

externally accessible end points. The tap points

between each resistive element are connected to the

wiper outputs with CMOS switches. A separate 8-bit

control register (WCR) independently controls the

wiper tap switches for each DP. Associated with

each wiper control register are four 8-bit non-volatile

memory data registers (DR) used for storing up to four

wiper settings. Writing to the wiper control register or

any of the non-volatile data registers is via a 2-wire

serial bus. On power-up, the contents of the first data

automatically loaded into its respective wiper control

registers.

The DP7269 can be used as a potentiometer or as a

two terminal, variable resistor. It is intended for circuit

level or system level adjustments in a wide variety of

applications. It is available in the -40ºC to 85ºC

industrial operating temperature ranges and offered in

a 24-lead SOIC and TSSOP package.

FUNCTIONAL DIAGRAM

SCL

SDA

2-WIRE BUS

INTERFACE

RH0 RH1

WIPER

CONTROL

REGISTERS

RW0

CONTROL

LOGIC

NONVOLATILE

DATA

REGISTERS

RL0 RL1

RW1

Characteristics subject to change without notice

Doc. No. MD-2123 Rev. D

1 Page

DP7269

ABSOLUTE MAXIMUM RATINGS(1)

Parameters

Temperature Under Bias

Storage Temperature

Voltage on Any Pin with Respect to VSS(1) (2)

VCC with Respect to Ground

Package Power Dissipation Capability (TA = 25ºC)

Lead Soldering Temperature (10secs)

Wiper Current

Ratings

-55 to +125

-65 to +150

-2.0 to +VCC + 2.0

-2.0 to +7.0

1.0

300

±6

Units

ºC

°C

ºC

RECOMMENDED OPERATING CONDITIONS

Parameters

VCC

Industrial Temperature

Ratings

+2.5 to +6

-40 to +85

Units

°C

POTENTIOMETER CHARACTERISTICS

(Over recommended operating conditions unless otherwise stated.)

Symbol

RPOT

Parameter

Potentiometer Resistance (100k)

Potentiometer Resistance (50k)

Potentiometer Resistance

Tolerance

RPOT Matching

Power Rating

Test Conditions

25°C, each pot

Limits

Min Typ. Max

100

±20

Units

VTERM

TCRPOT

TCRATIO

CH/CL/CW

Wiper Current

Wiper Resistance

Voltage on any RH or RL Pin

Resolution

Absolute Linearity (5)

Relative Linearity (6)

Temperature Coefficient of RPOT

Ratiometric Temp. Coefficient

Potentiometer Capacitances

Frequency Response

IW = ±3mA @ VCC = 3V

IW = ±3mA @ VCC = 5V

VSS = 0V

Rw(n)(actual)-R(n)(expected)(8)

Rw(n+1)-[Rw(n)+LSB](8)

(4)

RPOT = 50k (4)

±3

200 300

100 150

VSS

VCC

0.4

±1

±0.2

±300

10/10/25

0.4

LSB (7)

ppm/ºC

MHz

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this

specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.

(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.

(4) This parameter is tested initially and after a design or process change that affects the parameter.

(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.

(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-

meter. It is a measure of the error in step size.

(7) LSB = RTOT / 255 or (RH - RL) / 255, single pot

(8) n = 0, 1, 2, ..., 255

Characteristics subject to change without notice

Doc. No. MD-2123 Rev. D

3Pages

DP7269

SERIAL BUS PROTOCOL

The following defines the features of the 2-wire bus

protocol:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high will

be interpreted as a START or STOP condition.

The device controlling the transfer is a master,

typically a processor or controller, and the device

being controlled is the slave. The master will always

initiate data transfers and provide the clock for both

transmit and receive operations. Therefore, the

DP7269 will be considered a slave device in all

applications.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The DP7269 monitors the

SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are

fixed as 0101 for the DP7269 (see Figure 5). The

next four significant bits (A3, A2, A1, A0) are the

device address bits and define which device the

Master is accessing. Up to sixteen devices may be

individually addressed by the system. Typically, +5V

and ground are hard-wired to these pins to establish

the device's address.

After the Master sends a START condition and the

slave address byte, the DP7269 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address.

Acknowledge

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

Acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8

bits of data.

The DP7269 responds with an acknowledge after

receiving a START condition and its slave address. If

the device has been selected along with a write

operation, it responds with an acknowledge after

receiving each 8-bit byte.

When the DP7269 is in a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the

line for an acknowledge. Once it receives this

acknowledge, the DP7269 will continue to transmit

data. If no acknowledge is sent by the Master, the

device terminates data transmission and waits for a

STOP condition.

Write Operations

In the Write mode, the Master device sends the

START condition and the slave address information to

the Slave device. After the Slave generates an

acknowledge, the Master sends the instruction byte

that defines the requested operation of DP7269. The

instruction byte consist of a four-bit opcode followed

by two register selection bits and two pot selection

bits. After receiving another acknowledge from the

Slave, the Master device transmits the data to be

written into the selected register. The DP7269

acknowledges once more and the Master generates

the STOP condition, at which time if a nonvolatile data

internal programming cycle to non-volatile memory.

While this internal cycle is in progress, the device will

not respond to any request from the Master device.

Acknowledge Polling

The disabling of the inputs can be used to take

advantage of the typical write cycle time. Once the

stop condition is issued to indicate the end of the

host's write operation, the DP7269 initiates the

internal write cycle. ACK polling can be initiated

immediately. This involves issuing the start condition

followed by the slave address. If the DP7269 is still

busy with the write operation, no ACK will be returned.

If the DP7269 has completed the write operation, an

ACK will be returned and the host can then proceed

with the next instruction operation.

Write Protection

The Write Protection feature allows the user to protect

against inadvertent programming of the non-volatile

data registers. If the ¯W¯P¯ pin is tied to LOW, the data

registers are protected and become read only.

Similarly, the ¯W¯P¯ pin going low after start will interrupt

a nonvolatile write to data registers, while the ¯W¯P¯ pin

going low after an internal write cycle has stated will

have no effect on any write operation (see also

DP7409 or DP7259). The DP7269 will accept both

slave addresses and instructions, but the data registers

are protected from programming by the device’s failure

to send an acknowledge after data is received.

Doc. No. MD-2123 Rev. D

Characteristics subject to change without notice

6 Page

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