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DP7261 の電気的特性と機能

DP7261のメーカーはCOPAL ELECTRONICSです、この部品の機能は「Dual Digital Potentiometers」です。


製品の詳細 ( Datasheet PDF )

部品番号 DP7261
部品説明 Dual Digital Potentiometers
メーカ COPAL ELECTRONICS
ロゴ COPAL ELECTRONICS ロゴ 




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DP7261 Datasheet, DP7261 PDF,ピン配置, 機能
Dual Digital Potentiometers
(DP) with 256 Taps and SPI Interface
DP7261
FEATURES
Two linear-taper digital potentiometers
256 resistor taps per potentiometer
End to end resistance 50kŸ or 100kŸ
Potentiometer control and memory access via
SPI interface
Low wiper resistance, typically 100
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The DP7261 is two Digital Potentiometers
(DPs) integrated with control logic and 8 bytes of
NVRAM memory. Each DP consists of a series
of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the wiper
tap switches for each DP. Associated with each wiper
control register are four 8-bit non-volatile memory data
registers (DR) used for storing up to four wiper settings.
Writing to the wiper control register or any of the non-
volatile data registers is via a SPI serial bus. On power-
up, the contents of the first data register (DR0) for each
of the potentiometers is automatically loaded into its
respective wiper control register.
The DP7261 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
PIN CONFIGURATION
SOIC/TSSOP (W, Y)
SO 1
24 H¯¯O¯L¯D¯
A0 2
23 SCK
NC 3
22 NC
NC 4
21 NC
NC 5
20 NC
NC
6
DP
7261
19
NC
VCC 7
18 GND
RL0 8
17 RW1
RH0 9
16 RH1
RW0 10
¯C¯S¯ 11
15 RL1
14 A1
¯W¯P¯ 12
13 SI
FUNCTIONAL DIAGRAM
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
RH0 RH1
WP
A0
A1
HOLD
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0 RL1
RW0
RW1
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2122 Rev. D

1 Page





DP7261 pdf, ピン配列
DP7261
SERIAL BUS PROTOCOL
The DP7261 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the DP7261 to interface directly with
many of today's popular microcontrollers. The
DEVICE OPERATION
The DP7261 is two resistor arrays integrated with an
SPI serial interface logic, two 8-bit wiper control
registers and eight 8-bit, non-volatile memory data
registers. Each resistor array contains 255 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL).
RH and RL are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (RW) by a After the device is selected with
¯C¯S¯ going low the first byte will be received. The part
is accessed via the SI pin, with data being clocked in
on the rising edge of SCK. The first byte contains one
DP7261 contains an 8-bit instruction register. The
instruction set and the operation codes are detailed in
the instruction set table 3 on page 9.
of the six op-codes that define the operation to be
performed.
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper
control register. Data can be read or written to the
wiper control registers or the non-volatile memory
data registers via the SPI bus. Additional instructions
allows data to be transferred between the wiper
control registers and each respective potentiometer's
non-volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement"
mode.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
3
Doc. No. MD-2122 Rev. E


3Pages


DP7261 電子部品, 半導体
DP7261
POWER UP TIMING (1)(2)
Symbol Parameter
tPUR Power-up to Read Operation
tPUW Power-up to Write Operation
DP TIMING
Symbol Parameter
tWRPO
tWRL
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Min
5
5
WRITE CYCLE LIMITS
Symbol Parameter
tWR Write Cycle Time
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
Max
1
1
Units
ms
ms
Max Units
10 µs
10 µs
Max
5
Units
ms
Max
Units
Cycles/Byte
Years
V
mA
Figure 1. Synchronous Data Timing
VIH
CS
SCK
VIL
tCSS
VIH
VIL
VIH
SI
VIL
tWH
tSU tH
VALID IN
VOH
SO
VOL
HI-Z
tCS
tCSH
tWL
tRI
tFI
tV
tHO
tDIS
HI-Z
Note: Dashed Line = mode (1, 1)
Doc. No. MD-2122 Rev. E
6 © NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
DP7261

Dual Digital Potentiometers

COPAL ELECTRONICS
COPAL ELECTRONICS
DP7269

Dual Digital Potentiometers

COPAL ELECTRONICS
COPAL ELECTRONICS


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