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PDF IRMCK099 Data sheet ( Hoja de datos )
| Número de pieza | IRMCK099 | |
| Descripción | motor control IC | |
| Fabricantes | Infineon | |
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IRMCK099
Data Sheet
iMOTION™ motor control IC for single motor drive
Quality Requirement Category: Industry
Features
Ready-to-use solution for high efficiency variable speed drives
Pre-programmed motion control engine (MCE)
Sensor less field oriented control (FOC) of permanent magnet synchronous motors (PMSM)
Support for up to 31 sets of motor parameters
Current measurement based on single or leg shunt
Integrated oscillator, A/D converter, OP amps & comparators
Integrated protection features
Package: 5x5mm² QFN-32
Applications
Pumps & fans
Drones, multicopters
Home appliances
Any other PMSM drive
Description
The IRMCK099 combines the iMOTION™ motor control
engine (MCE) with all peripherals required to realize a
complete variable speed drive. The IRMCK099 does not
require algorithm programming and can be used in
combination with a µIPM™ or a discrete power stage.
The MCE implements sensor less field oriented control
using single or leg shunt current feedback and uses
space vector PWM with sinusoidal signals to provide
highest energy efficiency.
Data Sheet
Please read the Important Notice and Warnings at the end of this document
www.infineon.com/iMOTION
Revision 1.0
2014-12-18
1 page  
IRMCK099M
List of Figures
FIGURE 1. TYPICAL APPLICATION BLOCK DIAGRAM USING IRMCK099 ...................................................................................5
FIGURE 2. PINOUT OF IRMCK099 .............................................................................................................................................6
FIGURE 3. IRMCK099 BLOCK DIAGRAM....................................................................................................................................8
FIGURE 4. IRMCK099 LEG SHUNT CONNECTION DIAGRAM .....................................................................................................9
FIGURE 5. VOLTAGE DROOP AND S/H HOLD TIME ....................................................................................................................16
FIGURE 6. OP AMP OUTPUT CAPACITOR ...................................................................................................................................17
FIGURE 7. SYNC TIMING...........................................................................................................................................................18
FIGURE 8. FAULT TIMING ...........................................................................................................................................................19
FIGURE 9. ITRIP TIMING ...........................................................................................................................................................19
FIGURE 10. I2C TIMING .............................................................................................................................................................20
FIGURE 11. UART TIMING.........................................................................................................................................................21
FIGURE 12. CAPTURE TIMING ................................................................................................................................................22
FIGURE 13. JTAG TIMING .........................................................................................................................................................23
FIGURE 14. DIGITAL I/O STRUCTURE .......................................................................................................................................24
FIGURE 15. ANALOG I/O STRUCTURE ......................................................................................................................................24
FIGURE 16 ANALOG ANALOG INPUT STRUCTURE FOR AIN0/STBY.......................................................................................24
FIGURE 17. VSS PIN I/O STRUCTURE.......................................................................................................................................25
FIGURE 18. VDDCAP PIN I/O STRUCTURE ..............................................................................................................................25
FIGURE 19. VDD1 PIN I/O STRUCTURE ....................................................................................................................................25
4 www.irf.com
© 2014International Rectifier
December 18, 2014
5 Page 
IRMCK099M
Analog Output Interface
AOPWM1
Input/output, can be configured as 8-bit PWM output 1 with programmable carrier
frequency
AOPWM2
Input/output, can be configured as 8-bit PWM output 2 with programmable carrier
frequency
I2C Interface
SCL
SDA
Output, I2C clock output, can be configured to GPIO pins
Input/output, I2C Data line, can be configured to GPIO pins
Capture Interface
CAP
Capture Input, can be configured to GPIO pins
4.2 Motion Peripheral Interface Group
PWM
PWMUH
PWMUL
PWMVH
PWMVL
PWMWH
PWMWL
Output, PWM phase U high side gate signal, tri-state at power up until configured by
firmware
Output, PWM phase U low side gate signal, tri-state at power up until configured by
firmware
Output, PWM phase V high side gate signal, tri-state at power up until configured by
firmware
Output, PWM phase V low side gate signal, tri-state at power up until configured by
firmware
Output, PWM phase W high side gate signal, tri-state at power up until configured by
firmware
Output, PWM phase W low side gate signal, tri-state at power up until configured by
firmware
GATEKILL
GK
Input, upon assertion this sets all six PWM signals to off state according to setting of
active_pol register, pulled up by 49kOhm internal resistor
4.3 Analog Interface Group
IFB1+
IFB1-
IFB1O
Input, Operational amplifier positive input for single or leg shunt resistor current
sensing
Input, Operational amplifier negative input for single or leg shunt resistor current
sensing
Output, Operational amplifier output for single or leg shunt resistor current sensing
IFB2+
IFB2-
IFB2O
Input, Operational amplifier positive input for 2nd leg shunt resistor current sensing
Input, Operational amplifier negative input for 2nd leg shunt resistor current sensing
Output, Operational amplifier output for 2nd leg shunt resistor current sensing
AIN0/VSP
AIN1/VBUS
AIN2
AIN3
Input, Analog input channel 0 (0 – 1.2 V), also used for Standby Mode wake-up
Input, Analog input channel 1 (0 – 1.2 V), typically configured for DC bus voltage input
Input, Analog input channel 2 (0 – 1.2 V), needs to be pulled down to VSS if unused
Input, Analog input channel 3 (0 – 1.2 V), needs to be pulled down to VSS if unused
10 www.irf.com
© 2014International Rectifier
December 18, 2014
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IRMCK099.PDF ] | |
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