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74HCT139 の電気的特性と機能

74HCT139のメーカーはNXP Semiconductorsです、この部品の機能は「Dual 2-to-4 line decoder/demultiplexer」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HCT139
部品説明 Dual 2-to-4 line decoder/demultiplexer
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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74HCT139 Datasheet, 74HCT139 PDF,ピン配置, 機能
74HC139; 74HCT139
Dual 2-to-4 line decoder/demultiplexer
Rev. 4 — 11 December 2015
Product data sheet
1. General description
The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four
mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE).
When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data
input for a 1-to-4 demultiplexer application. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Input levels:
For 74HC139: CMOS level
For 74HCT139: TTL level
Demultiplexing capability
2 independent 2-to-4 decoders
Multifunction capability
Suitable for memory decoding, data routing or code conversion
Complies with JEDEC standard no. 7A
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC139D
40 C to +125 C SO16
74 HCT139D
74HC139DB
40 C to +125 C SSOP16
74HCT139DB
74HC139PW
40 C to +125 C TSSOP16
74HCT139PW
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1

1 Page





74HCT139 pdf, ピン配列
NXP Semiconductors
74HC139; 74HCT139
Dual 2-to-4 line decoder/demultiplexer
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Fig 4. Logic diagram (one decoder/demultiplexer)
5. Pinning information
5.1 Pinning
<
<
<
<
DDD
( 
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 (
$ 
< 
< 
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< 
< 
 <
 <
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DDG
Fig 5. Pin configuration SO16, SSOP16 and TSSOP16
5.2 Pin description
Table 2. Pin description
Symbol
1E, 2E
1A0, 1A1
1Y0, 1Y1, 1Y2, 1Y3
GND
2Y0, 2Y1, 2Y2, 2Y3
2A0, 2A1
VCC
Pin
1, 15
2, 3
4, 5, 6, 7
8
12, 11, 10, 9
14, 13
16
Description
enable input (active LOW)
address input
output (active LOW)
ground (0 V)
output (active LOW)
address input
positive supply voltage
74HC_HCT139
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 11 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 17


3Pages


74HCT139 電子部品, 半導体
NXP Semiconductors
74HC139; 74HCT139
Dual 2-to-4 line decoder/demultiplexer
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to
+85 C
Min Typ Max Min Max
ICC
supply current VI = VCC or GND; IO = 0 A;
-
- 8.0
-
VCC = 6.0 V
CI input
capacitance
- 3.5 -
-
80
-
74HCT139
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
2.0 1.6 -
2.0
-
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
- 1.2 0.8
-
0.8
VOH
VOL
II
IOZ
ICC
ICC
HIGH-level
output voltage
LOW-level
output voltage
input leakage
current
OFF-state
output current
supply current
additional
supply current
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
IO = 4 mA
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
IO = 4.0 mA
VI = VCC or GND;
VCC = 5.5 V
VI = VIH or VIL;
VO = VCC or GND;
VCC = 5.5 V
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; 1An inputs
4.4
3.98
-
-
-
-
-
-
4.5
4.32
0
0.15
-
-
-
70
-
-
0.1
0.26
0.1
0.5
8.0
252
4.4
3.84
-
-
-
-
-
-
-
-
0.1
0.33
1.0
5.0
80
315
per input pin; 2An inputs
- 70 252
-
315
per input pin; nE inputs
- 135 486 - 607.5
CI input
capacitance
- 3.5 -
-
-
Tamb = 40 C to Unit
+125 C
Min Max
- 160 A
- - pF
2.0 - V
- 0.8 V
4.4 - V
3.7 - V
- 0.1 V
- 0.4 V
- 1.0 A
- 10 A
- 160 A
- 343 A
- 343 A
- 661.5 A
- - pF
74HC_HCT139
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 11 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 17

6 Page



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