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PDF ATMEGA644PV Data sheet ( Hoja de datos )
| Número de pieza | ATMEGA644PV | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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8-bit Atmel Microcontroller with 16K/32K/64K Bytes
In-System Programmable Flash
ATmega164P/V-ATmega324P/V-ATmega644P/V
DATASHEET
Features
High-performance, Low-power Atmel® AVR® 8-bit Microcontroller
Advanced RISC Architecture
̶ 131 Powerful Instructions – Most Single-clock Cycle Execution
̶ 32 × 8 General Purpose Working Registers
̶ Fully Static Operation
̶ Up to 20 MIPS Throughput at 20 MHz
̶ On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
̶ 16K/32K/64K Bytes of In-System Self-programmable Flash program memory
̶ 512B/1K/2K Bytes EEPROM
̶ 1K/2K/4K Bytes Internal SRAM
̶ Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
̶ Data retention: 20 years at 85C/100 years at 25C(1)
̶ Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
̶ Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
̶ Boundary-scan Capabilities According to the JTAG Standard
̶ Extensive On-chip Debug Support
̶ Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
Interface
Peripheral Features
̶ Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
̶ One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
̶ Real Time Counter with Separate Oscillator
̶ Six PWM Channels
̶ 8-channel, 10-bit ADC
Differential mode with selectable gain at 1×, 10× or 200×
̶ Byte-oriented Two-wire Serial Interface
̶ Two Programmable Serial USART
̶ Master/Slave SPI Serial Interface
̶ Programmable Watchdog Timer with Separate On-chip Oscillator
̶ On-chip Analog Comparator
Atmel-8011R-AVR-ATmega164P/V-324P/V-644P/V-Datasheet_09/2015
1 page  
purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible
Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-
channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog
Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming and six software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other
chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer
continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize
switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional
nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program
can use any interface to download the application program in the application Flash memory. Software in the
Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-
While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The ATmega164P/324P/644P AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation
kits.
2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P
Table 2-1. Differences between ATmega164P and ATmega644P
Device
ATmega164P
Flash
16 Kbyte
EEPROM
512 Bytes
ATmega324P
32 Kbyte
1 Kbyte
ATmega644P
64 Kbyte
2 Kbyte
RAM
1 Kbyte
2 Kbyte
4 Kbyte
ATmega164P/V-324P/V-644P/V [DATASHEET]
Atmel-8011R-AVR--09/2015
5
5 Page 
4.3.1 SREG – Status Register
The AVR Status Register – SREG – is defined as:
Bit
0x3F (0x5F)
Read/Write
Initial Value
7
I
R/W
0
6
T
R/W
0
5
H
R/W
0
4
S
R/W
0
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of
the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by
hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the
instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the
operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T
can be copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD
arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V.
See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set
Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description”
for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the Register File:
One 8-bit output operand and one 8-bit result input
ATmega164P/V-324P/V-644P/V [DATASHEET]
Atmel-8011R-AVR--09/2015
11
11 Page | ||
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| PDF Descargar | [ Datasheet ATMEGA644PV.PDF ] | |
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